Hardware Preparation and Installation | Motorola MVME197LE specification

Hardware Preparation and Installation

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2-2	User’s Manual

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Motorola MVME197LE user manual Hardware Preparation and Installation

Contents

MVME197LE MVME197LE/D2 Restricted Rights Legend Preface Document Terminology BIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General Description Features Ote MVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements Equipment Required FCC Compliance Support Information Unpacking Instructions Hardware Preparation Hardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory Map Detailed I/O Memory Maps 108 BusSwitch Register Memory Map100 110 Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Dcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory Map Operating Instructions VMEchip2 Memory Map Sheet 1 Offset Operating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2 Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100 Operating Instructions PCCchip2 Memory Map Printer PE Interrupt Control Register $FFF42033 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer Busy Interrupt Control Register $FFF42034 Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 12. MK48T08 BBRAM, TOD Clock Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map Address Range Description Size Bytes 14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 01-W3869B03A VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 5000 Software Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description Mezzanine Address Bus Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Memory Array Flash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersPeripheral Resources Scsi Termination Local Peripheral Bus Timeout Watchdog TimerProcessor Bus Timeout Interrupt Sources MVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D Interconnections Ring Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index Numerics IN-2 IN-3 Index