VMEbus Memory Map, 01-W3869B03A, 5000 | Motorola MVME197LE instruction

Operating Instructions

4.		Sixteen bytes are reserved for the printed wiring assembly (PWA) number
		assigned to this board in ASCII format. This includes the 01-W prefix. This
		is for the main logic board if more than one board is required for a set.
		Additional boards in a set are defined by a structure for that set. For
3
3		example, for a 32 megabyte, 50 MHz MVME197LE board at revision A, the

PWA field contains:

01-W3869B03A

(The 12 characters are followed by four blanks.)

5.Four bytes contain the speed of the board in MHz. The first two bytes are the whole number of MHz and the second two bytes are fractions of MHz. For example, for a 50 MHz board, this field contains:

5000

6.Eight bytes are reserved for the Ethernet address. The address is stored in hexadecimal format, with the last two bytes not used. (Refer to the Ethernet Interface section for a more detailed description). If the board does not support Ethernet, this field is filled with zeros.

7.Growth space (195 bytes) is reserved. This pads the structure to an even 256 bytes. Board-specific items, such as mezzanine board PWA numbers, may go here.

8.The final one byte of the area is reserved for a checksum (as defined in the MVME197BUG 197Bug Debugging Package User’s Manual) for security and data integrity of the configuration area of the NVRAM. This data is stored in hexadecimal format.

VMEbus Memory Map

This section describes the mapping of local resources as viewed by VMEbus masters.

VMEbus Accesses to the Local Peripheral Bus

The VMEchip2 includes a user-programmable map decoder for the VMEbus to local peripheral bus interface. The map decoder allows the user to program the starting and ending address and the modifiers the MVME197 responds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-programmable map decoder for the GCSR (Global Control and Status Registers). The GCSR map decoder allows the user to program the starting address of the GCSR in the VMEbus short I/O space.

3-26	User’s Manual

Image 56

Motorola MVME197LE user manual VMEbus Memory Map, 01-W3869B03A, 5000, VMEbus Accesses to the Local Peripheral Bus

Contents

MVME197LE MVME197LE/D2 Restricted Rights Legend Preface Document Terminology BIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General Description Features Ote Characteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements Equipment Required FCC Compliance Support Information Unpacking Instructions Hardware Preparation Hardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory Map Detailed I/O Memory Maps BusSwitch Register Memory Map 100108 110 Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Dcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory Map Operating Instructions VMEchip2 Memory Map Sheet 1 Offset Operating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2 Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100 Operating Instructions PCCchip2 Memory Map Printer Fault Interrupt Control Register $FFF42031 Printer SEL Interrupt Control Register $FFF42032Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034 Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 Accesses may be 8-bit or 32-bit, but not 16-bit 11 C710 Scsi Memory Map12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes Data Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 VMEbus Accesses to the Local Peripheral Bus VMEbus Memory Map01-W3869B03A 5000 Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description Bus Data Bus 256 BusSwitch MC88110 Address Data MUX AddressMezzanine Address Bus Memory Array Onboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Printer Interface Ethernet Interface Programmable Tick Timers Peripheral ResourcesScsi Interface Scsi Termination Watchdog Timer Processor Bus TimeoutLocal Peripheral Bus Timeout Interrupt Sources MVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D Interconnections Ring Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index Numerics IN-2 IN-3 Index