S3F80P5_UM_ REV1.00 CONTROL REGISTERS
SYM — System Mode Register DEH Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 − − x x x 0 0
Read/Write R/W − − R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Tri-State External Interface Control Bit (note1)
0 Normal operation (disable tri-state operation)
1 Set external interface lines to high impedance (enable tri-state operation)
.6 and .5 Not used for S3F80P5 (note2)
.4− .2 Fast Interrupt Level Selection Bits (note3)
0 0 0 IRQ0
0 0 1 IRQ1
0 1 0 IRQ2
0 1 1 IRQ3
1 0 0 IRQ4
1 0 1 Not used for S3F80P5
1 1 0 IRQ6
1 1 1 IRQ7
.1 Fast Interrupt Enable Bit (note4)
0 Disable fast interrupt processing
1 Enable fast interrupt processing
.0 Global Interrupt Enable Bit (note5)
0 Disable global interrupt processing
1 Enable global interrupt processing
NOTES:
1. Because an external interface is not implemented for the S3F80P5, SYM.7 must always be "0".
2. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during
normal operation, a system malfunction may occur.
3. You can select only one interrupt level at a time for fast interrupt processing.
4. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2−SYM.4.
5. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
to SYM.0).
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