RESET S3F80P5_UM_ REV1.00
SOURCES TO RELEASE STOP MODE
Stop mode is released when following sources go active:
— System Reset by Internal Power-On Reset (IPOR)
— External Interrupt (INT0-INT5)
— SED & R circuit
Using IPOR to Release STOP Mode
Stop mode is released when the system reset signal goes active by internal power-on reset (IPOR). All system
and peripheral control registers are reset to their default hardware values and contents of all data registers are
unknown states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in reset address.
Using an External Interrupt to Release STOP Mode
External interrupts can be used to release stop mode. When RESET Control Bit is set to ‘0’ (smart option @
03FH) and external interrupt is enabled, S3F80P5 is released from stop mode and generates reset signal. On the
other hand, when RESET Control Bit are set to ‘1’ (smart option @ 03FH), S3F80P5 is only released from stop
mode and does not generate reset signal. To wake-up from stop mode by external interrupt from INT0 to INT5,
external interrupt should be enabled by setting corresponding control registers or instructions.
Please note the following conditions for Stop mode release:
— If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged.
— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation
stabilization interval. To do this, you must make the appropriate control and clock settings before entering
Stop mode.
— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains
unchanged and the currently selected clock value is used.
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