CONTROL REGISTERS S3F80P5_UM_ REV1.00
CLKCON — System Clock Control Register D4H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7− .5 Not used for S3F80P5
.4 and .3 CPU Clock (System Clock) Selection Bits (1)
0 0
fOSC/16
0 1
fOSC/8
1 0
fOSC/2
1 1
fOSC (non-divided)
.2– .0 Subsystem Clock Selection Bits (2)
1 0 1 Not used for S3F80P5.
Other value Select main system clock (MCLK)
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The
S3F80P5 uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
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