S3F80P5_UM_ REV1.00 LOW VOLTAGE DETECTOR
15 LOW VOLTAGE DETECTOR
OVERVIEW
The S3F80P5 micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and
LVD_FLAG detection of power voltage. The S3F80P5 has two options in LVD and LVD_FLAG voltage level
according to the operating frequency to be set by smart option (Refer to the page 2-4).
Operating Frequency 8MHz:
• Low voltage detect level for Backup Mode and Reset (LVD): 1.65V (Typ) ± 50mV
• Low voltage detect level for Flash Flag Bit (LVD_FLAG): 1.88, 1.98, 2.53, 2.73V (Typ) ± 100mV
After power-on, LVD block is always enabled. LVD block is only disable when executed STOP instruction. The
LVD block of S3F80P5 consists of two comparators and a resistor string. One of comparators is for LVD
detection, and the other is for LVD_FLAG detection.
LVD
LVD circuit supplies two operating modes by one comparator: back-up mode input and system reset input. The
S3F80P5 can enter the back-up mode and generate the reset signal by the LVD level (note1) detection using
LVD circuit. When LVD circuit detects the LVD level in falling power, S3F80P5 enters the Back-up mode.
Back-up mode input automatically creates a chip stop state. When LVD circuit detects the LVD level in rising
power, the system reset occurs. This reset by LVD circuit is one of the S3F80P5 reset sources. (Refer to the
page 8-3 for more.)
LVD FLAG
The other comparator’s output makes LVD indicator flag bit ‘1’ or ‘0’. That is used to indicate low voltage level.
When the power voltage is below the LVD_FLAG level, the bit 0 of LVDCON register is set ‘1’. When the power
voltage is above the LVD_FLAG level, the bit 0 of LVDCON register is set ‘0’ automatically. LVDCON.0 can be
used flag bit to indicate low battery in IR application or others.
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