CONTROL REGISTERS S3F80P5_UM_ REV1.00
P2PND — Port 2 External Interrupt Pending Register E6H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.0 P2.0 External Interrupt (INT4) Pending Flag Bit
0 No P2.0 external interrupt pending (when read)
1 P2.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt
rending flag (P2PND.0−7) has no effect.
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