Samsung S3F80P5, S3F80P5X (EI)external interrupt enable

RESET S3F80P5_UM_ REV1.00

Watchdog Timer

STOP

(EI)external interrupt enable

P0&P2.0

(INT0-INT5)

STOP

LVD

IPOR

RESET

RESET Contorl Bit '1'

STOP

RESET Contorl Bit '1'

*RESET Control Bit : smart option bit[0]@03FH

Figure 8-1. RESET Sources of the S3F80P5

1. The rising edge detection of LVD circuit while rising of VDD passes the level of V .

LVD

2. When POR circuit detects VDD below V , reset is generated by internal power-on reset.

POR

3. Basic Timer over-flow for watchdog timer. See the chapter 10. Basic Timer and Timer 0 for more

understanding.

4. When RESET Control Bit (smart option @ 03FH) is set to ‘0’ and chip is in stop mode, external interrupt input

by P0 and P2.0 generates the reset signal.

5. When RESET Control Bit (smart option @ 03FH) are set to ‘0’ and chip is in stop mode or abnormal state, the

falling edge input of P0 generates the reset signal regardless of external interrupt enable/disable.

8-2

Contents

Main USERS MANUAL S3F80P5X Important Notice Preface Table of Contents Part I Programming Model Chapter 1 Product Overview Chapter 2 Address Spaces Chapter 3 Addressing Modes Chapter 4 Control Registers Chapter 5 Interrupt Structure Table of Contents(Continued) Chapter 6 Instruction Set Chapter 7 Clock and Power Circuit Chapter 8 RESET Page Chapter 12 Counter A Chapter 13 Timer 2 Chapter 14 Embedded Flash Memory Interface Table of Contents Page List of Figures List of Figures List of Figures (Conclude) Page List of Tables List of Tables(Conclude) 1 S3C8/S3F8-SERIES MICROCONTROLLERS S3F80P5 MICROCONTROLLER FEATURES Page PIN ASSIGNMENTS S3C8 0P5 Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package) Page PRODUCT OVERVIEW S3F80P5_UM_ REV1.00 PIN CIRCUITS 1-6 Figure 1-3. Pin Circuit Type 1 (Port 0) Figure 1-4. Pin Circuit Type 2 (Port 1) Figure 1-5. Pin Circuit Type 2 (Port 2) Figure 1-6. Pin Circuit Type 4 (P3.0) Figure 1-7. Pin Circuit Type 5 (P3.1) 2 PROGRAM MEMORY S3F80P5_UM_ REV1.00 ADDRESS SPACE 2-3 Figure 2-2. Smart Option Page REGISTER ARCHITECTURE Figure 2-3. Internal Register File Organization Page Page Page Page Page Page REGISTER ADDRESSING ADDRESS SPACE S3F80P5_UM_ REV1.00 Figure 2-10. Register File Addressing 2-14 ~~ Page S3F80P5_UM_ REV1.00 ADDRESS SPACE Figure 2-12. 4-Bit Working Register Addressing 2-17 Figure 2-13. 4-Bit Working Register Addressing Example Page S3F80P5_UM_ REV1.00 ADDRESS SPACE Figure 2-15. 8-Bit Working Register Addressing Example 2-19 SYSTEM AND USER STACKS Page Page 3 Figure 3-1. Register Addressing Figure 3-2. Working Register Addressing Page INDIRECT REGISTER ADDRESSING MODE (Continued) Figure 3-4. Indirect Register Addressing to Program Memory INDIRECT REGISTER ADDRESSING MODE (Continued) ~ ~ ~ ~ Figure 3-5. Indirect Working Register Addressing to Register File ADDRESSING MODES S3F80P5_UM_ REV1.00 INDIRECT REGISTER ADDRESSING MODE (Continued) 3-6 Figure 3-6. Indirect Working Register Addressing to Program or Data Memory + ~ ~ ~ ~ ADDRESSING MODES S3F80P5_UM_ REV1.00 + ~ ~ Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset S3F80P5_UM_ REV1.00 ADDRESSING MODES INDEXED ADDRESSING MODE (Continued) + ~~ Figure 3-9. Indexed Addressing to Program or Data Memory Page Page Page + Page 4 Page Page Page S3F80P5_UM_ REV1.00 CONTROL REGISTERS FLAGS 4-5 - System Flags Register Bit Identifier Reset Value Read/Write Figure 4-1. Register Description Format BTCON Basic Timer Control Register D3H Set1 Bank0 CACON Counter A Control Register F3H Set1 Bank0 CLKCON System Clock Control Register D4H Set1 Bank0 EMT External Memory Timing Register (NOTE) FEH Set1 Bank0 FLAGS FMCON FMSECH Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 FMSECL Flash Memory Sector Address Register(Low Byte) EDH Set1 Bank1 FMUSR IMR IPH Instruction Pointer (High Byte) DAH Set1 Bank0 IPL Instruction Pointer (Low Byte) DBH Set1 Bank0 IPR IRQ LVDCON LVD Control Register E0H Set1 Bank1 Page P0CONH Port 0 Control Register (High Byte) E8H Set1 Bank0 P0CONL Port 0 Control Register (Low Byte) E9H Set1 Bank0 P0INT Port 0 External Interrupt Enable Register F1H Set1 Bank0 P0PND P0PUR Port 0 Pull-up Resistor Enable Register E7H Set1 Bank0 P1CONH Port 1 Control Register (High Byte) EAH Set1 Bank0 P1CONL Port 1 Control Register (Low Byte) EBH Set1 Bank0 P1OUTPU Port 1 Output Pull-up Resistor Enable Register F2H Set1 Bank1 P2CONL P2INT Port 2 External Interrupt Enable Register E5H Set1 Bank0 P2OUTMD Port 2 Output Mode Selection Register F3H Set1 Bank1 P2PND P2PUR Port 2 Pull-up Resistor Enable Register EEH Set1 Bank0 P3CON Port 3 Control Register EFH Set1 Bank0 Page Page PP RESETID Reset Source Indicating Register F0H Set1 Bank1 RP0 RP1 SPL Stack Pointer (Low Byte) D9H Set1 Bank0 STOPCON Stop Control Register FBH Set1 Bank0 SYM T0CON T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 5 Page Figure 5-2. S3F80P5 Interrupt Structure Page Page Page Page Page Page Page Page INTERRUPT STRUCTURE S3F80P5_UM_ REV1.00 5-12 Figure 5-8. Interrupt Priority Register (IPR) Page Page Page Page Page Page 6 Page Page Page Page Page C Z S V D Page Page Page Page Page Page ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR Bit XOR CALL CCF Complement Carry Flag CLR COM Complement CP CPIJE CPIJNE Page DA DEC DECW DI Disable Interrupts DIV Divide (Unsigned) DJNZ EI ENTER EXIT IDLE Idle Operation INC INCW Increment Word IRET JP Jump JR Page LD LDB Load Bit Page LDC/LDE LDCD/LDED Load Memory and Decrement LDCI/LDEI Load Memory and Increment LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT Next NOP OR POP POPUD Pop User Stack (Decrementing) POPUI Pop User Stack (Incrementing) PUSH PUSHUD Push User Stack (Decrementing) PUSHUI Push User Stack (Incrementing) RCF RET Return RL Rotate Left RLC RR RRC SB0 SB1 SBC Subtract With Carry SCF Set Carry Flag SRA Shift Right Arithmetic SRP/SRP0/SRP1 Set Register Pointer STOP SUB Subtract SWAP TCM TM WFI XOR Page 7 Page Page Page Page Page 8 (EI)external interrupt enable S3F80P5_UM_ REV1.00 RESET 8-3 fosc Figure 8-2. RESET Block Diagram of the S3F80P5 Page Page Page Page POWER-DOWN MODES Page Figure 8-8. Timing Diagram for Back-up Mode Input in Stop Mode Page Page Page Page Page Page Page Page Page Page 9 Page Page Page 10 Page Page Page S3F80P5_UM_ REV1.00 BASIC TIMER and TIMER 0 10-5 Figure 10-2. Timer 0 Control Register (T0CON) Figure 10-3. Timer 0 DATA Register (T0DATA) Page Page Page Figure 10-7. Basic Timer and Timer 0 Block Diagram Page Page Page 11 Page Page Figure 11-3. Timer 1 Block Diagram Page Page 12 Figure 12-1. Counter A Block Diagram Page Page Figure 12-4. Counter A Output Flip-Flop Waveforms in Repeat Mode Page Page Page 13 Page Page TIMER 2 S3F80P5_UM_ REV1.00 Figure 13-3. Timer 2 Block Diagram 13-4 Page Page 14 ISPTM (ON-BOARD PROGRAMMING) SECTOR Page Page FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) Page SECTOR ERASE Page Page Page PROGRAMMING Page Figure 14-10. Program Flowchart in a User Program Mode Page Page READING HARD LOCK PROTECTION Page 15 Resistor String Page 16 Page Page Page Page Page Page Page Page Page Page Page S3F80P5_UM_ REV1.00 MECHANICAL DATA 17 17-1 The S3F80P5 micro-controller is currently available in a 24-pin SOP and SDIP package. 24-SOP-375 Figure 17-1. 24-Pin SOP Package Mechanical Data 24-SDIP-300 Figure 17-2. 24-Pin SDIP Package Mechanical Data 18 S3F80P5 FLASH MCU S3F80P5_UM_ REV1.00 18-2 S3C8 0P5 Figure 18-1. Pin Assignment Diagram (24-Pin SOP/SDIP Package) Page Page 19 Emulator [ SK-1200(RS-232,USB) or OPENIce I-500(RS-232) ] S3F80P5_UM_ REV1.00 ELECTRICAL DATA 19-3 ++ + TB80PB Rev1 In-Circuit Emulator (SK-1200,OPENIce I -500) Table 19-1. Setting of the Jumper in TB80PB Page DEVELOPMENT TOOLS S3F80P5_UM_ REV1.00 19-6 25 26 J2 Figure 19-3. 50-Pin Connector Pin Assignment for User System Page SPW-uni AS-pro US-pro GW-PRO2