S3F80P5_UM_ REV1.00 INTERRUPT STRUCTURE
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source.
The system-level control points in the interrupt structure are, therefore:
• Global interrupt enable and disable (by EI and DI instructions or by a direct manipulation of SYM.0)
• Interrupt level enable/disable settings (IMR register)
• Interrupt level priority settings (IPR register)
• Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing the part of your application program that handles the interrupt processing, be sure to
include the necessary register file address (register pointer) information.
Interrupt Request Register
(Read-only)
IRQ0-IRQ7
Interrupts
Interrupt Mask
Register
Polling
Cycle
Interrupt Priority
Register
Global Interrupt Control
(EI, DI or SYM.0 manipulation)
S
R
Q
EI
Vector
Interrupt
Cycle
nRESET
Figure 5-4. Interrupt Function Diagram
5-7