RESET S3F80P5_UM_ REV1.00
SYSTEM RESET OPERATION
System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal
CPU and peripheral modules. This procedure brings the S3F80P5 into a known operating status. To allow time
for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum
time interval after the power supply comes within tolerance. The minimum required reset operation for an
oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are then reset to
their default hardware values (See Tables 8-2).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watch-dog function (Basic Timer) is enabled.
— Port 0,2 and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.
— Peripheral control and data register settings are disabled and reset to their default hardware values.
(See Table 8-2.)
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in reset
address is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing '1010B' to the upper nibble of BTCON. But we recommend you should use it to
prevent the chip malfunction.
8-14