S3F80P5_UM_ REV1.00 RESET
8 RESET
OVERVIEW
Resetting the MCU is the function to start processing by generating reset signal using several reset schemes.
During reset, most control and status are forced to initial values and the program counter is loaded from the reset
vector. In case of S3F80P5, reset vector can be changed by smart option. (Refer to the page 2-3 or 13-4).
RESET SOURCES
The S3F80P5 has five-different system reset sources as following
– Watch Dog Timer (WTD): When watchdog timer enables in normal operating, a reset is generated
whenever the basic timer overflow occurs.
– Low Voltage Detect (LVD): When VDD is changed in condition for LVD operation in the normal operating
mode, reset occurs.
– Internal Power-ON Reset (IPOR): When VDD is changed in condition for IPOR operation, a reset is
generated.
– External Interrupt (INT0-INT5): When RESET Control Bit is set to ‘0’ (smart option @ 03FH) and chip is
in stop mode, if external interrupt is enabled, external interrupts by P0 and P2.0 generate the reset signal.
– STOP Error Detection & Recovery (SED&R): When RESET Control Bit is set to ‘0’ (smart option bit [7]
@ 03FH) and MCU is in stop or abnormal state, the falling edge input of P0 generates the reset signal
regardless of external interrupt enable or disable.
8-1