PRODUCT OVERVIEW S3F80P5_UM_ REV1.00
FEATURES CPU
• SAM8 RC CPU core
Memory
• Program memory:
- 18-Kbyte Internal Flash Memory
- 10 years data retention
- Endurance: 10,000 Erase/Program cycles
- Byte Programmable
- User programmable by ‘LDC’ instruction
• Executable memory: 1K-byte RAM
• Data memory: 272-byte general purpose RAM
Instruction Set
• 78 instructions
• IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
• 500 ns at 8-MHz fOSC (minimum)
Interrupts
• 17 interrupt sources with 14 vectors
and 7 levels.
I/O Ports
• Two 8-bit I/O ports (P0, P1), one 1-bit (P2) and
2-bit (P3) for a total of 19 bit-programmable pins
(24-SOP, 24-SDIP)
Carrier Frequency Generator
• One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
Basic Timer and Timer/Counters
• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function
• One 8-bit timer/counter (Timer 0) with three
operating modes: Interval mode, Capture and
PWM mode.
• One 16-bit timer/counter (Timer1) with two
operating modes: Interval and Capture mode.
• One 16-bit timer/counter (Timer2) with two
operating modes: Interval and Capture mode.
Back-up Mode
• When VDD is lower than VLVD, LVD is ‘ON’ and the
chip enters Back-up mode to block oscillation
Low Voltage Detect Circuit
• Low voltage detect to get into Back-up mode and
Reset
1.65V (Typ) ± 50mV
• Low voltage detect to control LVD_Flag bit
1.88, 1.98, 2.53, 2.73V (Typ) ± 100mV (selectable)
• LVD-Reset is enabled in the operating mode:
When the voltage at VDD is falling down and
passing VLVD, the chip goes into back-up mode.
The voltage at VDD is rising up, the reset pulse is
generated at “VDD> VLVD”.
• LVD is disabled in the stop mode: If the voltage at
VDD is not falling down to VPOR, the reset pulse is
not generated.
Operating Temperature Range
• -25°C to + 85 °C
Operating Voltage Range
• 1.60V to 3.6V at 1~8MHz
Package Types
• 24-pin SOP
• 24-pin SDIP
1-2