CONTROL REGISTERS S3F80P5_UM_ REV1.00
FLAGS — System Flags Register D5H Set1 Bank0
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Reset Value x x x x x x 0 0
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Addressing Mode Register addressing mode only
.7 Carry Flag Bit (C)
0 Operation does not generate a carry or borrow condition
1 Operation generates a carry-out or borrow into high-order bit 7
.6 Zero Flag Bit (Z)
0 Operation result is a non-zero value
1 Operation result is zero
.5 Sign Flag Bit (S)
0 Operation generates a positive number (MSB = "0")
1 Operation generates a negative number (MSB = "1")
.4 Overflow Flag Bit (V)
0 Operation result is ≤ +127 or ≥ –128
1 Operation result is > +127 or < –128
.3 Decimal Adjust Flag Bit (D)
0 Add operation completed
1 Subtraction operation completed
.2 Half-Carry Flag Bit (H)
0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
.1 Fast Interrupt Status Flag Bit (FIS)
0 Interrupt return (IRET) in progress (when read)
1 Fast interrupt service routine in progress (when read)
.0 Bank Address Selection Flag Bit (BA)
0 Bank 0 is selected
1 Bank 1 is selected
4-10