Programming

FIFO Mode

Ch0

Ch1

Ch2

Ch3

Sample ordering in FIFO buffer

The samples are re-named for better readability. A0 is sample 0 of channel 0, C4 is sample 4 of channel 2, ...

The following example shows how to sort the channel data when using 4 channels in FIFO mode:

for (i = 0; i < lBufferSizeInSamples; i+=4)

{

FIFOBuffer[i + 0] = Data[0][i/4]; FIFOBuffer[i + 2] = Data[1][i/4]; FIFOBuffer[i + 1] = Data[2][i/4]; FIFOBuffer[i + 3] = Data[3][i/4];

}

Sample format

The sample format in FIFO mode does not differ from the one of the standard (non FIFO) mode. Please refer to the relating passage concerning the sample format in the standard acquisition chapter.

(c) Spectrum GmbH

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Image 53

Spectrum Brands MI.61XX manual Programming

Contents

English version October 5 MI.61xxPage Software Driver Installation Hardware InstallationIntroduction Software Programming the Board Fifo ModeAnalog Outputs Standard generation modes Option Extra I/O Option Gated ReplaySynchronization Option Appendix Preface IntroductionGeneral Information Preface Introduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Introduction Additional options Starhub Spectrum type plate Hardware information Block diagram Technical Data Order information Dynamic ParametersHardware informationIntroduction Filter System Requirements Hardware InstallationInstalling the board in the system Installing a board with extra I/O Option -XMF Installing a board with digital inputs/outputs Mounting the wired boards Installing multiple boards synchronized by starhubHooking up the boards Only use the included flat ribbon cables Installing multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Adding boards to the Windows NT driver Windows NT Overview Linux Now it is possible to access the board using this device Installing the deviceDriver info Automatic load of the driver Software Overview SoftwareFirst Test with SBench Software Header files ++ Driver InterfaceMicrosoft Visual C++ Linux Gnu C National Instruments LabWindows/CVI Other Windows C/C++ compilersDriver functions Include Drivers Function SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetData Spectrum GmbH Type definition Delphi Pascal Programming InterfaceInclude Driver Examples Delphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Programming the Board Error handlingOverview Register tables Initialization Example for error checkingStarting the automatic initialization routine PCI Register Hardware version Installed memoryDate of production Serial number Used interrupt line Installed features and optionsUsed type of driver Driver version Example program for the board initialization Powerdown and resetSpcpcimemsize Spcpciserialno Channel Selection Analog OutputsImportant note on channels selection Disabling the outputs Output Amplifiers Setting up the outputsOutput offset Register Value Direction Description Amplitude range Output Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Maximum memsize Standard generation modes ProgrammingMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samples Starting with interrupt driven mode Starting without interrupt classic modeCommand register ProgrammingStandard generation modes Writing data with SpcSetData Data organizationValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer value Sample format Standard modeBit Standard Mode General Information Fifo ModeBackground Fifo Write Speed Limitations Software Buffers Programming Fifo ModeTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffers Buffer processing Fifo Mode ProgrammingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards == Maxbuf Example Fifo generation modeSpcfifostart Spcfifowait Programming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Trigger modes and appendant registers Example for setting up the software triggerSoftware trigger External TTL trigger Edge triggers Example on how to set up the board for positive TTL triggerTrigger modes and appendant registers Positive TTL trigger Positive and negative TTL trigger Option Multiple Replay Standard ModeOutput modes Trigger modes Trigger modes Option Multiple Replay Resulting start delays Option Gated Replay General information and trigger delayOption Gated Replay Value Direction Description Allowed trigger modes Example programExternal TTL edge trigger Spctriggermode Tmttlpos Digital I/Os Option Extra I/OChannel direction Transfer Data Analog Outputs Option Extra I/O Analog OutputsProgramming example Different synchronization options Synchronization OptionSynchronization with option cascading Synchronization with option starhub Set up the board parameters Setup order for the different synchronization optionsExample of board setup for three boards Write Data to on-board memory output boards only Example of board #2 set as trigger master Define the boards for trigger master3a Define synchronization or trigger Define the remaining boards as trigger slaves Example board number 0 is clock master Define the board for clock masterDefine the remaining boards as clock slaves Arm the boards for synchronization Wait for the end of the measurement Start all of the trigger master boardsRead data from the on-board memory acquisition boards only Example for data reading 2a Write first data for output boards Allocate the Fifo software buffersSpcsyncmasterfifo Spcsyncslavefifo As trigger slaves General information Additions for synchronizing different boardsCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Board type 3122 3120 Setting up the clock divider40 MS/s Board type 3025 3131 Delay in standard non Fifo modes Resulting delays using different boards or speedsDelay in Fifo mode Additions for equal boards with different sample rates Error name Value hex Value dec Error description Error CodesAppendix Appendix Pin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF Extra I/O with internal connector Option -XIO Pin assignment of the internal multipin connectorD14 D12 D10 D15 D13 D11