Trigger modes Option Multiple Replay | Spectrum Brands MI.61XX

	Trigger modes							Option Multiple Replay

	Resulting start delays

	Sample rate	Output Mode	Activated channels				external TTL trigger	ext. TTL trigger with activated
								synchronization
			0	1	2	3
	< 5 MHz	Standard or FIFO	x				8 samples	10 samples

	> 5 MHz	Standard or FIFO	x				24 samples	26 samples

	< 2.5 MHz	Standard or FIFO	x	x			5 samples	6 samples
	> 2.5 MHz	Standard or FIFO	x	x			14 samples	15 samples

	< 5 MHz	Standard	x		x		8 samples	10 samples

	> 5 MHz	Standard	x		x		24 samples	26 samples
	< 2.5 MHz	FIFO	x		x		5 samples	6 samples

	> 2.5 MHz	FIFO	x		x		14 samples	15 samples

	< 2.5 MHz	Standard	x	x	x	x	5 samples	6 samples
	> 2.5 MHz	Standard	x	x	x	x	14 samples	15 samples

	< 1.25 MHz	FIFO	x	x	x	x	3.5 samples (falling clock edge)	3.5 samples (falling clock edge)

	> 1.25 MHz	FIFO	x	x	x	x	8.5 samples (falling clock edge)	8.5 samples (falling clock edge)

The following example shows how to set up the board for Multiple Replay in standard mode. The setup would be similar in FIFO mode, but the memsize register would not be used.

SpcSetParam (hDrv,	SPC_MULTI,	1);	// Enables Multiple Replay
SpcSetParam (hDrv,	SPC_POSTTRIGGER,	1024);	// Set the segment size to 1024 samples	to 4096 samples
SpcSetParam (hDrv,	SPC_MEMSIZE,	4096);	// Set the total memsize for replaying	to 4096 samples
			// so that actually four segments will	be replayed
SpcSetParam (hDrv, SPC_TRIGGERMODE,		TM_TTLPOS);	// Set the triggermode to external TTL mode (rising edge)

62	MI.61xx Manual

Image 62

Spectrum Brands MI.61XX manual Trigger modes Option Multiple Replay, Resulting start delays

Contents

MI.61xx English version October 5Page Introduction Hardware InstallationSoftware Driver Installation Software Analog Outputs Fifo ModeProgramming the Board Standard generation modes Synchronization Option Option Gated ReplayOption Extra I/O Appendix General Information IntroductionPreface Preface Introduction Different models of the MI.61xx seriesMI.6110 MI.6111 Extra I/O Option -XIO Additional optionsExtra I/O Option -XMF Starhub Introduction Additional options Spectrum type plate Block diagram Technical Data Hardware information Hardware informationIntroduction Dynamic ParametersOrder information Filter System Requirements Hardware InstallationInstalling the board in the system Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMF Hooking up the boards Installing multiple boards synchronized by starhubMounting the wired boards Only use the included flat ribbon cables Installing multiple synchronized boards Interrupt Sharing Software Driver InstallationSoftware Driver Installation Version control InstallationWindows Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driver Linux Overview Driver info Installing the deviceNow it is possible to access the board using this device Automatic load of the driver First Test with SBench SoftwareSoftware Overview Software Microsoft Visual C++ ++ Driver InterfaceHeader files Linux Gnu C Driver functions Other Windows C/C++ compilersNational Instruments LabWindows/CVI Include Drivers Function SpcSetData Windows Function SpcSetParamFunction SpcSetParam Function SpcGetData Spectrum GmbH Include Driver Delphi Pascal Programming InterfaceType definition Examples Delphi Pascal Programming Interface VBA for Excel Examples Visual Basic Programming InterfaceVisual Basic Examples Visual Basic Programming Interface Overview Error handlingProgramming the Board Register tables Starting the automatic initialization routine Example for error checkingInitialization PCI Register Date of production Installed memoryHardware version Serial number Used type of driver Installed features and optionsUsed interrupt line Driver version Spcpcimemsize Powerdown and resetExample program for the board initialization Spcpciserialno Important note on channels selection Analog OutputsChannel Selection Disabling the outputs Output offset Setting up the outputsOutput Amplifiers Register Value Direction Description Amplitude range Output Filters Filter SpecificationsMaximum Output Range Programming Standard generation modesGeneral description Maximum posttrigger in MSamples Standard generation modes ProgrammingMaximum memsize Minimum and stepsize of memsize and posttrigger in samples Command register Starting without interrupt classic modeStarting with interrupt driven mode ProgrammingStandard generation modes Value ’start’ as a 32 bit integer value Data organizationWriting data with SpcSetData Value ’len’ as a 32 bit integer value Sample format Standard modeBit Standard Mode Background Fifo Write Fifo ModeGeneral Information Speed Limitations Theoretical maximum sample rate PCI Bus Throughput Programming Fifo ModeSoftware Buffers 60040 Read out the number of available Fifo buffers Analog acquisition or generation boards Fifo Mode ProgrammingBuffer processing Digital I/O 701x or 702x or pattern generator boards Spcfifostart Example Fifo generation mode== Maxbuf Spcfifowait Programming Standard internal sample rate Clock generationInternally generated sample rate External clocking Using plain quartz with no PLLExternal reference clock Maximum external samplerate in MS/s Direct external clockMinimum external sample rate CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 External clock with dividerExample Software trigger Example for setting up the software triggerTrigger modes and appendant registers External TTL trigger Trigger modes and appendant registers Example on how to set up the board for positive TTL triggerEdge triggers Positive TTL trigger Positive and negative TTL trigger Output modes Standard ModeOption Multiple Replay Trigger modes Resulting start delays Trigger modes Option Multiple Replay Option Gated Replay General information and trigger delayOption Gated Replay Value Direction Description External TTL edge trigger Example programAllowed trigger modes Spctriggermode Tmttlpos Channel direction Option Extra I/ODigital I/Os Transfer Data Analog Outputs Option Extra I/O Analog OutputsProgramming example Synchronization with option cascading Synchronization OptionDifferent synchronization options Synchronization with option starhub Example of board setup for three boards Setup order for the different synchronization optionsSet up the board parameters Write Data to on-board memory output boards only 3a Define synchronization or trigger Define the boards for trigger masterExample of board #2 set as trigger master Define the remaining boards as trigger slaves Define the remaining boards as clock slaves Define the board for clock masterExample board number 0 is clock master Arm the boards for synchronization Read data from the on-board memory acquisition boards only Start all of the trigger master boardsWait for the end of the measurement Example for data reading Spcsyncmasterfifo Allocate the Fifo software buffers2a Write first data for output boards Spcsyncslavefifo As trigger slaves Calculating the clock dividers Additions for synchronizing different boardsGeneral information 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx 40 MS/s Setting up the clock dividerBoard type 3122 3120 Board type 3025 3131 Delay in Fifo mode Resulting delays using different boards or speedsDelay in standard non Fifo modes Additions for equal boards with different sample rates Appendix Error CodesError name Value hex Value dec Error description Appendix Pin assignment of the multipin cable Pin assignment of the multipin connectorExtra I/O with external connectorOption -XMF D14 D12 D10 Pin assignment of the internal multipin connectorExtra I/O with internal connector Option -XIO D15 D13 D11