Spectrum Brands MI.61XX - page 75

Synchronization (Option) The setup order for the different synchronization options

(c) Spectrum GmbH 75

Setting up the clock divider

The clock divider can easily be set by the following register. Please keep in mind that the divider must be set for every synchronized board

to have synchronization working correctly. For more details on the board’s clocking modes please refer to the according chapter in this ma-

nual.

Available divider values

Although this setup is looking very complicated at first glance, it is not really difficult to set up different boards to work synchronously with the

same speed. To give you an idea on how to setup the boards the calculations are shown in the following two examples.

Each example contains of a simple setup of two synchronized boards. It is assumed that all of the available channels on the dedicated boards

have been activated.

Example calculation with synchronous speed where slave clock is divided

Example calculation with synchronous speed where master clock is divided

Register Value Direction Description

SPC_CLOCKDIV 20040 r/w Extra clock divider for synchronizing different boards.

1 2 4 8 101620405080100200

400 500 800 1000 2000

Board type 3122 3120

Channels available 8 x 12 bit A/D 2 x 12 bit A/D

Desired sample rate 10 MS/s 10 MS/s

Enabled channels per module 4 2

Sum sample rate 40 MS/s 20 MS/s

Therefore this board is set up

to be the clockmaster.

Sync speed 40 MS/s 40 MS/s

Clock divider 1 2

Divided sum clock 40 MS/s 20 MS/s

Enabled channels per module 4 2

Conversion speed 10 MS/s 10 MS/s

Board type 3025 3131

Channels available 2 x 12 bit A/D 4 x 12 bit A/D

Desired sample rate 20 MS/s 20 MS/s

Enabled channels per module 1 2

Sum sample rate 20 MS/s 40 MS/s

Therefore this board is set up

to be the clockmaster.

Sync speed 40 MS/s 40 MS/s

Clock divider 2 1

Divided sum clock 20 MS/s 40 MS/s

Enabled channels per module 1 2

Conversion speed 20 MS/s 20 MS/s

Contents

Main Page Page Page Page Introduction Preface General Information Page Additional options Extra I/O (Option -XMF) Extra I/O (Option -XIO) Starhub The Spectrum type plate Introduction Hardware information (c) Spectrum GmbH 11 Hardware information Block diagram Technical Data 12 MI.61xx Manual Hardware information Introduction Dynamic Parameters Order information Hardware Installation System Requirements Warnings ESD Precautions Cooling Precautions Installing a board with digital inputs/outputs Installing a board with extra I/O (Option -XMF) Installing multiple boards synchronized by starhub Installing multiple synchronized boards Software Driver Installation Interrupt Sharing Windows 98 Page Windows 2000 Page Windows XP Page Windows NT Adding boards to the Windows NT driver Linux Overview Page Software Software Overview First Test with SBench C/C++ Driver Interface Header files Microsoft Visual C++ Linux Gnu C Other Windows C/C++ compilers National Instruments LabWindows/CVI Page Page Delphi (Pascal) Programming Interface Type definition Include Driver Examples Page Visual Basic Programming Interface Include Driver Visual Basic Examples VBA for Excel Examples Page Programming the Board Register tables Programming examples Error handling Initialization Starting the automatic initialization routine PCI Register Hardware version Date of production Serial number Maximum possible sample rate Installed memory Installed features and options Used interrupt line Used type of driver Powerdown and reset Analog Outputs Channel Selection Important note on channels selection Disabling the outputs Setting up the outputs Output Amplifiers Output offset Maximum Output Range Output Filters Standard generation modes General description Singleshot mode Continuous Mode Posttrigger Mode Page Starting without interrupt (classic mode) Starting with interrupt driven mode Data organization Writing data with SpcSetData Sample format FIFO Mode General Information Background FIFO Write Speed Limitations Programming Software Buffers Buffer processing FIFO mode Example FIFO generation mode Data organization Sample format Clock generation Internally generated sample rate Standard internal sample rate Using plain quartz with no PLL External reference clock External clocking Direct external clock External clock with divider Trigger modes and appendant registers General Description Software trigger External TTL trigger Edge triggers Page Option Multiple Replay Output modes Standard Mode FIFO Mode Trigger modes Trigger modes Option Multiple Replay Resulting start delays Option Gated Replay Output modes Standard Mode FIFO Mode Trigger modes Example program Option Extra I/O Digital I/Os Channel direction Transfer Data Analog Outputs Programming example Synchronization (Option) The different synchronization options Synchronization with option cascading Synchronization with option starhub The setup order for the different synchronization options Setup Order for use with standard (non FIFO) mode and equally clocked boards Page Page Page Setup synchronization for use with FIFO mode and equally clocked boards Page Additions for synchronizing different boards SumSampleRateNSampleRate=NActChPerModuleN ----------------------------------------------------------------------------------= ClockDivider SyncSpeed SampleRateNActChPerModuleN Page Additions for equal boards with different sample rates Resulting delays using different boards or speeds = ResultingDelay ClockMasterDelay ClockSlaveDelayN Appendix Error Codes Appendix Error Codes Pin assignment of the multipin connector Extra I/O with external connector(Option -XMF) Pin assignment of the multipin cable Pin assignment of the internal multipin connector Extra I/O with internal connector (Option -XIO)