External TTL trigger

External TTL trigger	Trigger modes and appendant registers

Positive and negative TTL trigger

This mode is for detecting the rising and falling edges of an ex- ternal TTL signal. The board will trigger on the first rising or falling edge that is detected after starting the board. The next triggere- vent will then be detected, if the actual recording/replay has fi- nished and the board is armed and waiting for a trigger again.

Register		Value	Direction	Description
SPC_TRIGGERMODE		40000	r/w	Sets the triggermode for the board.
	TM_TTLBOTH	20030	Sets the trigger mode for external TTL trigger to detect positive and negative edges.

60	MI.61xx Manual

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Spectrum Brands MI.61XX manual External TTL trigger, Positive and negative TTL trigger

Contents

MI.61xx English version October 5Page Hardware Installation Software Driver InstallationIntroduction Software Fifo Mode Programming the BoardAnalog Outputs Standard generation modes Option Gated Replay Option Extra I/OSynchronization Option Appendix Introduction PrefaceGeneral Information Preface Different models of the MI.61xx series MI.6110 MI.6111Introduction Additional options Extra I/O Option -XMFExtra I/O Option -XIO Starhub Introduction Additional options Spectrum type plate Block diagram Technical Data Hardware information Dynamic Parameters Order informationHardware informationIntroduction Filter Hardware Installation Installing the board in the systemSystem Requirements Installing a board with digital inputs/outputs Installing a board with extra I/O Option -XMF Installing multiple boards synchronized by starhub Mounting the wired boardsHooking up the boards Only use the included flat ribbon cables Installing multiple synchronized boards Software Driver Installation Software Driver InstallationInterrupt Sharing Installation WindowsVersion control Driver Update Windows Software Driver Installation Windows Windows XP Windows XP Windows NT Adding boards to the Windows NT driver Linux Overview Installing the device Now it is possible to access the board using this deviceDriver info Automatic load of the driver Software Software OverviewFirst Test with SBench Software ++ Driver Interface Header filesMicrosoft Visual C++ Linux Gnu C Other Windows C/C++ compilers National Instruments LabWindows/CVIDriver functions Include Drivers Function SpcSetParam Function SpcSetParamFunction SpcSetData Windows Function SpcGetData Spectrum GmbH Delphi Pascal Programming Interface Type definitionInclude Driver Examples Delphi Pascal Programming Interface Visual Basic Programming Interface Visual Basic ExamplesVBA for Excel Examples Visual Basic Programming Interface Error handling Programming the BoardOverview Register tables Example for error checking InitializationStarting the automatic initialization routine PCI Register Installed memory Hardware versionDate of production Serial number Installed features and options Used interrupt lineUsed type of driver Driver version Powerdown and reset Example program for the board initializationSpcpcimemsize Spcpciserialno Analog Outputs Channel SelectionImportant note on channels selection Disabling the outputs Setting up the outputs Output AmplifiersOutput offset Register Value Direction Description Amplitude range Filter Specifications Maximum Output RangeOutput Filters Standard generation modes General descriptionProgramming Standard generation modes Programming Maximum memsizeMaximum posttrigger in MSamples Minimum and stepsize of memsize and posttrigger in samples Starting without interrupt classic mode Starting with interrupt driven modeCommand register ProgrammingStandard generation modes Data organization Writing data with SpcSetDataValue ’start’ as a 32 bit integer value Value ’len’ as a 32 bit integer value Standard mode Bit Standard ModeSample format Fifo Mode General InformationBackground Fifo Write Speed Limitations Programming Fifo Mode Software BuffersTheoretical maximum sample rate PCI Bus Throughput 60040 Read out the number of available Fifo buffers Fifo Mode Programming Buffer processingAnalog acquisition or generation boards Digital I/O 701x or 702x or pattern generator boards Example Fifo generation mode == MaxbufSpcfifostart Spcfifowait Programming Clock generation Internally generated sample rateStandard internal sample rate Using plain quartz with no PLL External reference clockExternal clocking Direct external clock Minimum external sample rateMaximum external samplerate in MS/s External clock with divider ExampleCHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 Example for setting up the software trigger Trigger modes and appendant registersSoftware trigger External TTL trigger Example on how to set up the board for positive TTL trigger Edge triggersTrigger modes and appendant registers Positive TTL trigger Positive and negative TTL trigger Standard Mode Option Multiple ReplayOutput modes Trigger modes Resulting start delays Trigger modes Option Multiple Replay General information and trigger delay Option Gated ReplayOption Gated Replay Value Direction Description Example program Allowed trigger modesExternal TTL edge trigger Spctriggermode Tmttlpos Option Extra I/O Digital I/OsChannel direction Transfer Data Analog Outputs Programming exampleAnalog Outputs Option Extra I/O Synchronization Option Different synchronization optionsSynchronization with option cascading Synchronization with option starhub Setup order for the different synchronization options Set up the board parametersExample of board setup for three boards Write Data to on-board memory output boards only Define the boards for trigger master Example of board #2 set as trigger master3a Define synchronization or trigger Define the remaining boards as trigger slaves Define the board for clock master Example board number 0 is clock masterDefine the remaining boards as clock slaves Arm the boards for synchronization Start all of the trigger master boards Wait for the end of the measurementRead data from the on-board memory acquisition boards only Example for data reading Allocate the Fifo software buffers 2a Write first data for output boardsSpcsyncmasterfifo Spcsyncslavefifo As trigger slaves Additions for synchronizing different boards General informationCalculating the clock dividers 20xx 30xx 31xx 40xx 45xx 60xx 61xx 70xx 72xx Setting up the clock divider Board type 3122 312040 MS/s Board type 3025 3131 Resulting delays using different boards or speeds Delay in standard non Fifo modesDelay in Fifo mode Additions for equal boards with different sample rates Error Codes Error name Value hex Value dec Error descriptionAppendix Appendix Pin assignment of the multipin connector Extra I/O with external connectorOption -XMFPin assignment of the multipin cable Pin assignment of the internal multipin connector Extra I/O with internal connector Option -XIOD14 D12 D10 D15 D13 D11

Positive and negative TTL trigger

Register

TM_TTLBOTH