Spectrum Brands MI.61XX

60 MI.61xx Manual

External TTL trigger Trigger modes and appendant registers

Positive and negative TTL trigger

This mode is for detecting the rising and falling edges of an ex-

ternal TTL signal. The board will trigger on the first rising or falling

edge that is detected after starting the board. The next triggere-

vent will then be detected, if the actual recording/replay has fi-

nished and the board is armed and waiting for a trigger again.

SPC_TRIGGERMODE 40000 r/w Sets the triggermode for the board.

TM_TTLBOTH 20030 Sets the trigger mode for external TTL trigger to detect positive and negative edges.

Contents

Main Page Page Page Page Introduction Preface General Information Page Additional options Extra I/O (Option -XMF) Extra I/O (Option -XIO) Starhub The Spectrum type plate Introduction Hardware information (c) Spectrum GmbH 11 Hardware information Block diagram Technical Data 12 MI.61xx Manual Hardware information Introduction Dynamic Parameters Order information Hardware Installation System Requirements Warnings ESD Precautions Cooling Precautions Installing a board with digital inputs/outputs Installing a board with extra I/O (Option -XMF) Installing multiple boards synchronized by starhub Installing multiple synchronized boards Software Driver Installation Interrupt Sharing Windows 98 Page Windows 2000 Page Windows XP Page Windows NT Adding boards to the Windows NT driver Linux Overview Page Software Software Overview First Test with SBench C/C++ Driver Interface Header files Microsoft Visual C++ Linux Gnu C Other Windows C/C++ compilers National Instruments LabWindows/CVI Page Page Delphi (Pascal) Programming Interface Type definition Include Driver Examples Page Visual Basic Programming Interface Include Driver Visual Basic Examples VBA for Excel Examples Page Programming the Board Register tables Programming examples Error handling Initialization Starting the automatic initialization routine PCI Register Hardware version Date of production Serial number Maximum possible sample rate Installed memory Installed features and options Used interrupt line Used type of driver Powerdown and reset Analog Outputs Channel Selection Important note on channels selection Disabling the outputs Setting up the outputs Output Amplifiers Output offset Maximum Output Range Output Filters Standard generation modes General description Singleshot mode Continuous Mode Posttrigger Mode Page Starting without interrupt (classic mode) Starting with interrupt driven mode Data organization Writing data with SpcSetData Sample format FIFO Mode General Information Background FIFO Write Speed Limitations Programming Software Buffers Buffer processing FIFO mode Example FIFO generation mode Data organization Sample format Clock generation Internally generated sample rate Standard internal sample rate Using plain quartz with no PLL External reference clock External clocking Direct external clock External clock with divider Trigger modes and appendant registers General Description Software trigger External TTL trigger Edge triggers Page Option Multiple Replay Output modes Standard Mode FIFO Mode Trigger modes Trigger modes Option Multiple Replay Resulting start delays Option Gated Replay Output modes Standard Mode FIFO Mode Trigger modes Example program Option Extra I/O Digital I/Os Channel direction Transfer Data Analog Outputs Programming example Synchronization (Option) The different synchronization options Synchronization with option cascading Synchronization with option starhub The setup order for the different synchronization options Setup Order for use with standard (non FIFO) mode and equally clocked boards Page Page Page Setup synchronization for use with FIFO mode and equally clocked boards Page Additions for synchronizing different boards SumSampleRateNSampleRate=NActChPerModuleN ----------------------------------------------------------------------------------= ClockDivider SyncSpeed SampleRateNActChPerModuleN Page Additions for equal boards with different sample rates Resulting delays using different boards or speeds = ResultingDelay ClockMasterDelay ClockSlaveDelayN Appendix Error Codes Appendix Error Codes Pin assignment of the multipin connector Extra I/O with external connector(Option -XMF) Pin assignment of the multipin cable Pin assignment of the internal multipin connector Extra I/O with internal connector (Option -XIO)