Process, 59000 198000 | Texas Instruments TMS320 DSP specs

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Execution Time

Execution time should be expressed in instruction cycles whereas the period expressed in microseconds. Worst-case execution time must be accompanied with a precise description of the run-time assumptions required to reproduce this upper bound. For example, placement of code and data in internal or external memory, placement of specified buffers in dual-access or single access on-chip memory, etc. In particular, the worst-case execution time must be accompanied by a table of memory requirements (described above) necessary to achieve the quoted execution time. Note that the entries in this table are not required to be constants; they may be functions of the algorithm'sinstance creation parameters.

Operation	Period	Worst-Case Cycles/Period
process()	22500 μs	198000

In some cases, an algorithm'sworst-case execution time is a periodic function of the frame number. Suppose, for example, that an audio encoder consumes 10 milliseconds frames of data at a time but only outputs encoded data on every 20 milliseconds. In this case, the encoder'sworst-case execution time on even frames will differ (perhaps significantly) from the worst-case execution time for odd numbered frames; the output of data only occurs on odd frames. In these situations, it is important to characterize the worst-case execution time for each frame; otherwise, system integrators may (falsely) conclude that an algorithm will not be able to be combined with others.

All such algorithms must characterize their periodic execution time requirements by filling in the table below; the number of Cycles/Period columns can be any finite number M. The worst-case number in the Cycles/PeriodN column must be the worst-case number of cycles that can occur on frame number k * M + N, where k is any positive integer.

Operation	Period	Cycles/Period0	Cycles/Period1
process()	22500 μs	59000	198000

SPRU352G –June 2005 –Revised February 2007	Algorithm Performance Characterization	43
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Texas Instruments TMS320 DSP manual Process, 59000 198000

Contents

Rules and Guidelines Users Guide Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Guideline n Related DocumentationText Conventions Rule n Overview Rules for TMS320C5x Rules for TMS320C6x Scope of the Standard Requirements of the Standard Rules and Guidelines Intentional Omissions Goals of the Standard Frameworks System Architecture Core Run-Time Support Algorithms General Programming Guidelines Rule Use of C LanguageThreads and Reentrancy Threads Reentrancy Preemptive vs. Non-Preemptive Multitasking Example Data Memory Data Memory Scratch versus Persistent Memory Spaces Scratch vs Persistent Memory Allocation Guideline Algorithm versus Application ROM-ability Program MemorySection Name Purpose Use of Peripherals Use of Peripherals Interfaces and Modules Algorithms Packaging Algorithm Component Model Implementation Fir.h Interfaces and Modules External Identifiers Module Initialization and Finalization Naming ConventionsModule Instance Objects Run-Time Object Creation and Deletion Design-Time Object Creation Example Module Module Configuration Multiple Interface Support Description Required Interface InheritanceSummary Element Algorithms Algorithms Object Code Packaging Debug Verses Release Header Files Moduleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance Characterization External Heap MemorySize Static Local and Global Data Memory Stack Memory Data Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not Enough Execution Timeline for Two Periodic Tasks Execution Time Model 198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register Types Data Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte Ordering CSR Field Use Type Register ConventionsStatus Register Register Use Type TMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Example Relocatability SSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy General TMS320C24xx Guidelines TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA Resource Algorithm and Framework Overview Logical Channel Requirements for the Use of the DMA Resource Data Transfer Synchronization Data Transfer Properties DMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIs Device Independent DMA Optimization Guideline Submitting DMA Transfer Requests 13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers 14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers Non-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm Synchronization Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization Rules General Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library DSP/BIOS Run-time Support Library Books Bibliography Submit Documentation Feedback Glossary of Terms Glossary Glossary of Terms Glossary of Terms Important Notice