Use of Peripherals | Texas Instruments TMS320 DSP guide

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Use of Peripherals

Rule 5

Algorithms must characterize their ROM-ability; i.e., state whether or not they are ROM-able.

Obviously, self-modifying Code is not ROM-able. We do not require that no algorithm employ self-modifying Code; we only require documentation of the ROM-ability of an algorithm. It is also worth pointing out that if self-modifying Code is used, it must be done "atomically," i.e., with all interrupts disabled; otherwise this Code would fail to be reentrant.

2.6Use of Peripherals

To ensure the interoperability of eXpressDSP-compliant algorithms, it is important that algorithms never directly access any peripheral device.

Rule 6

Algorithms must never directly access any peripheral device. This includes, but is not limited to on-chip DMAs, timers, I/O devices, and cache control registers. Note, however, algorithms can utilize the DMA resource by implementing the IDMA2 interface on C64x and C5000 devices, and the IDMA3 interface on C64x+ devices using the EDMA3 controller. See Chapter 6 for details.

In order for an algorithm to be framework-independent, it is important that no algorithm directly calls any device interface to read or write data. All data produced or consumed by an algorithm must be explicitly passed to the algorithm by the client. For example, no algorithm should call a device-independent I/O library function to get data; this is the responsibility of the client or framework.

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General Programming Guidelines

SPRU352G –June 2005 –Revised February 2007

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Texas Instruments TMS320 DSP manual Use of Peripherals

Contents

Users Guide Rules and Guidelines Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Read This First Intended AudienceDocument Overview Related Documentation Text ConventionsRule n Guideline n Overview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6x Rules and Guidelines Requirements of the Standard Goals of the Standard Intentional Omissions System Architecture Frameworks Algorithms Core Run-Time Support General Programming Guidelines Use of C Language Threads and ReentrancyThreads Rule Preemptive vs. Non-Preemptive Multitasking Reentrancy Example Data Memory Data Memory Memory Spaces Scratch versus Persistent Scratch vs Persistent Memory Allocation Algorithm versus Application Guideline Program Memory ROM-abilitySection Name Purpose Use of Peripherals Use of Peripherals Algorithm Component Model Interfaces and Modules Algorithms Packaging Interfaces and Modules Implementation Fir.h External Identifiers Naming Conventions Module Initialization and FinalizationModule Instance Objects Design-Time Object Creation Run-Time Object Creation and Deletion Module Configuration Example Module Multiple Interface Support Interface Inheritance SummaryElement Description Required Algorithms Algorithms Packaging Object Code Header Files Debug Verses Release Moduleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution Time Heap Memory ExternalSize Stack Memory Static Local and Global Data Memory Data Bss Object files Size Interrupt Latency Execution TimeMips Is Not Enough Operation Execution Time Model Execution Timeline for Two Periodic Tasks Process 19800059000 198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register Types Use of Floating Point TMS320C6xxx Rules and GuidelinesEndian Byte Ordering Data Models Register Conventions Status RegisterRegister Use Type CSR Field Use Type Interrupt Latency TMS320C54xx Rules and GuidelinesProgram Models TMS320C54xx Rules and Guidelines Status Registers ST0 Field Name Use TypeST1 Field Name Use Type TMS320C55x Rules and Guidelines Stack ArchitecturePmst Field Name Use Type Relocatability Example SSP Status Bits ST2 Field Name Use TypeST3 Field Name Use Type Homy TMS320C24xx Guidelines General TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer Requests Overview Algorithm and Framework Requirements for the Use of the DMA Resource Logical Channel Data Transfer Properties Data Transfer Synchronization Abstract Interface DMA GuidelineDMA Rule Resource Characterization Data Transfers bytes FrequencyAverage Maximum Runtime APIs Strong Ordering of DMA Transfer Requests Submitting DMA Transfer Requests Device Independent DMA Optimization Guideline Cache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and Guidelines Minimizing Logical Channel Reconfiguration Overhead Addressing Automatic Endianism Conversion IssuesInter-Algorithm Synchronization Non-Preemptive System Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA Rules General Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library Bibliography Books Submit Documentation Feedback Glossary Glossary of Terms Glossary of Terms Glossary of Terms Important Notice