Inter-Algorithm Synchronization | Texas Instruments TMS320 DSP

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Inter-Algorithm Synchronization

It is important to notice that preemptive systems might have groups of algorithms that execute with the same priority. A well-designed DMA manager would assign the same physical channels to algorithms at the same priority level to avoid the scenarios described in Section 6.15.4 and Section 6.15.5. This, of course, requires at least one physical channel for each priority level, which might not always be the case.

In summary, sharing a DMA device among algorithms at different priorities can be accomplished in several different ways. In the end, it is the system integrator'schoice based on its available resources.

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Use of the DMA Resource

SPRU352G –June 2005 –Revised February 2007

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Texas Instruments TMS320 DSP manual Inter-Algorithm Synchronization

Contents

Users Guide Rules and Guidelines Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Document Overview Read This FirstIntended Audience Rule n Related DocumentationText Conventions Guideline n Overview Scope of the Standard Rules for TMS320C5x Rules for TMS320C6x Rules and Guidelines Requirements of the Standard Goals of the Standard Intentional Omissions System Architecture Frameworks Algorithms Core Run-Time Support General Programming Guidelines Threads Use of C LanguageThreads and Reentrancy Rule Preemptive vs. Non-Preemptive Multitasking Reentrancy Example Data Memory Data Memory Memory Spaces Scratch versus Persistent Scratch vs Persistent Memory Allocation Algorithm versus Application Guideline Section Name Purpose Program MemoryROM-ability Use of Peripherals Use of Peripherals Algorithm Component Model Interfaces and Modules Algorithms Packaging Interfaces and Modules Implementation Fir.h External Identifiers Module Instance Objects Naming ConventionsModule Initialization and Finalization Design-Time Object Creation Run-Time Object Creation and Deletion Module Configuration Example Module Multiple Interface Support Element Interface InheritanceSummary Description Required Algorithms Algorithms Packaging Object Code Header Files Debug Verses Release Moduleversvendorvariant.1arch Algorithm Performance Characterization Data Memory Program Memory Interrupt Latency Execution Time Size Heap MemoryExternal Stack Memory Static Local and Global Data Memory Data Bss Object files Size Mips Is Not Enough Interrupt LatencyExecution Time Operation Execution Time Model Execution Timeline for Two Periodic Tasks 59000 198000 Process198000 Submit Documentation Feedback DSP-Specific Guidelines CPU Register Types Register Types Endian Byte Ordering Use of Floating PointTMS320C6xxx Rules and Guidelines Data Models Register Use Type Register ConventionsStatus Register CSR Field Use Type Program Models Interrupt LatencyTMS320C54xx Rules and Guidelines TMS320C54xx Rules and Guidelines ST1 Field Name Use Type Status RegistersST0 Field Name Use Type Pmst Field Name Use Type TMS320C55x Rules and GuidelinesStack Architecture Relocatability Example SSP ST3 Field Name Use Type Status BitsST2 Field Name Use Type Homy TMS320C24xx Guidelines General TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Use of the DMA Resource Submitting DMA Transfer Requests Overview Algorithm and Framework Requirements for the Use of the DMA Resource Logical Channel Data Transfer Properties Data Transfer Synchronization DMA Rule Abstract InterfaceDMA Guideline Average Maximum Resource CharacterizationData Transfers bytes Frequency Runtime APIs Strong Ordering of DMA Transfer Requests Submitting DMA Transfer Requests Device Independent DMA Optimization Guideline Cache Coherency Issues for Algorithm Producers 13 C6xxx Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers 14 C55x Specific DMA Rules and Guidelines Inter-Algorithm Synchronization Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Non-Preemptive System Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules Performance Characterization Rules DMA Rules General Guidelines DMA Guidelines Submit Documentation Feedback DSP/BIOS Run-time Support Library Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library Bibliography Books Submit Documentation Feedback Glossary Glossary of Terms Glossary of Terms Glossary of Terms Important Notice