Glossary of Terms | Texas Instruments TMS320 DSP specification

www.ti.com

Glossary of Terms

Scheduling — The process of deciding what thread should execute next on a particular CPU. It is usually also taken as involving the context switch to that thread.

Scheduling Latency — The maximum time that a "ready" thread can be delayed by a lower priority thread.

Scratch Memory — Memory that can be overwritten without loss; i.e., prior contents need not be saved and restored after each use.

Scratch Register — A register that can be overwritten without loss; i.e., prior contents need not be saved and restored after each use.

Thread — The program state managed by the operating system that defines a logically independent sequence of program instructions. This state may be as little as the Program Counter (PC) value but often includes a large portion of the CPU'sregister set.

SPRU352G –June 2005 –Revised February 2007

Glossary

87

Submit Documentation Feedback

Image 87

Texas Instruments TMS320 DSP manual Glossary of Terms

Contents

Rules and Guidelines Users Guide Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Read This First Intended AudienceDocument Overview Guideline n Related DocumentationText Conventions Rule n Overview Rules for TMS320C5x Rules for TMS320C6x Scope of the Standard Requirements of the Standard Rules and Guidelines Intentional Omissions Goals of the Standard Frameworks System Architecture Core Run-Time Support Algorithms General Programming Guidelines Rule Use of C LanguageThreads and Reentrancy Threads Reentrancy Preemptive vs. Non-Preemptive Multitasking Example Data Memory Data Memory Scratch versus Persistent Memory Spaces Scratch vs Persistent Memory Allocation Guideline Algorithm versus Application Program Memory ROM-abilitySection Name Purpose Use of Peripherals Use of Peripherals Interfaces and Modules Algorithms Packaging Algorithm Component Model Implementation Fir.h Interfaces and Modules External Identifiers Naming Conventions Module Initialization and FinalizationModule Instance Objects Run-Time Object Creation and Deletion Design-Time Object Creation Example Module Module Configuration Multiple Interface Support Description Required Interface InheritanceSummary Element Algorithms Algorithms Object Code Packaging Debug Verses Release Header Files Moduleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance Characterization Heap Memory ExternalSize Static Local and Global Data Memory Stack Memory Data Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not Enough Execution Timeline for Two Periodic Tasks Execution Time Model Process 19800059000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register Types Data Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte Ordering CSR Field Use Type Register ConventionsStatus Register Register Use Type Interrupt Latency TMS320C54xx Rules and GuidelinesProgram Models TMS320C54xx Rules and Guidelines Status Registers ST0 Field Name Use TypeST1 Field Name Use Type TMS320C55x Rules and Guidelines Stack ArchitecturePmst Field Name Use Type Example Relocatability SSP Status Bits ST2 Field Name Use TypeST3 Field Name Use Type Homy General TMS320C24xx Guidelines TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA Resource Algorithm and Framework Overview Logical Channel Requirements for the Use of the DMA Resource Data Transfer Synchronization Data Transfer Properties Abstract Interface DMA GuidelineDMA Rule Resource Characterization Data Transfers bytes FrequencyAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIs Device Independent DMA Optimization Guideline Submitting DMA Transfer Requests 13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers 14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers Non-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm Synchronization Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization Rules General Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library DSP/BIOS Run-time Support Library Books Bibliography Submit Documentation Feedback Glossary of Terms Glossary Glossary of Terms Glossary of Terms Important Notice