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TMS320C28x Rules and Guidelines

5.7.2 Program Models

Only large memory model is supported for the program memory. So no special program memory requirements are needed for this processor. Just to reemphasize the point, all the program code must be completely relocatable and must not necessarily require placement in on-chip memory.

5.7.3 Register Conventions

This section describes the rules and guidelines that apply to the use of the TMS320C28x on-chip registers. Note that any register that is not described here must not be accessed by an algorithm; e.g., IMR, IFR, and peripheral control and status register. The table below describes all the registers that may be accessed by an algorithm.

Register	Use	Type
AL	Expressions, argument passing, and returns 16-bit results from functions	Scratch (local)
AH	Expressions and argument passing	Scratch (local)
XAR0	Pointers and expressions	Scratch (local)
XAR1	Pointers and expressions	Preserve (local)
XAR2	Pointers, expressions, and frame pointers	Preserve (local)
XAR3	Pointers and expressions	Preserve (local)
XAR4	Pointers, expressions, argument passing, and returns 16- and 22-bit	Scratch (local)
	pointer values from functions
XAR5	Pointers, expressions, and arguments	Scratch (local)
XAR6	Pointers and expressions	Scratch (local)
XAR7	Pointers, expressions, indirect calls, and branches	Scratch (local)
SP	Stack pointer	Preserve (local)
T	Multiply and shift expressions	Scratch (local)
TL	Multiply and shift expressions	Scratch (local)
PL	Multiply expressions and Temp variables	Scratch (local)
PH	Multiply expressions and Temp variables	Scratch (local)
DP	Data page pointer	Scratch (local)

5.7.4 Status Registers

The TMS320C28x device contains two-status registers: ST0 and ST1. Each status register is further divided into several distinct fields that may be accessed separately using special instructions like SETC, CLRC, SPM, etc.

ST0 Field Name	Use	Type
OVC/OVCU	Overflow counter	Scratch (local)
PM	Produce shift mode	Init (local)
V	Overflow flag	Scratch (local)
N	Negative flag	Scratch (local)
Z	Zero flag	Scratch (local)
C	Carry flag	Scratch (local)
TC	Test/Control flag	Scratch (local)
OVM	Overflow mode	Scratch (local)
SXM	Sign extension mode	Scratch (local)

SPRU352G –June 2005 –Revised February 2007	DSP-Specific Guidelines	59
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Texas Instruments TMS320 DSP manual XAR0

Contents

Rules and Guidelines Users Guide Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Document Overview Read This FirstIntended Audience Guideline n Related DocumentationText Conventions Rule n Overview Rules for TMS320C5x Rules for TMS320C6x Scope of the Standard Requirements of the Standard Rules and Guidelines Intentional Omissions Goals of the Standard Frameworks System Architecture Core Run-Time Support Algorithms General Programming Guidelines Rule Use of C LanguageThreads and Reentrancy Threads Reentrancy Preemptive vs. Non-Preemptive Multitasking Example Data Memory Data Memory Scratch versus Persistent Memory Spaces Scratch vs Persistent Memory Allocation Guideline Algorithm versus Application Section Name Purpose Program MemoryROM-ability Use of Peripherals Use of Peripherals Interfaces and Modules Algorithms Packaging Algorithm Component Model Implementation Fir.h Interfaces and Modules External Identifiers Module Instance Objects Naming ConventionsModule Initialization and Finalization Run-Time Object Creation and Deletion Design-Time Object Creation Example Module Module Configuration Multiple Interface Support Description Required Interface InheritanceSummary Element Algorithms Algorithms Object Code Packaging Debug Verses Release Header Files Moduleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance Characterization Size Heap MemoryExternal Static Local and Global Data Memory Stack Memory Data Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not Enough Execution Timeline for Two Periodic Tasks Execution Time Model 59000 198000 Process198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register Types Data Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte Ordering CSR Field Use Type Register ConventionsStatus Register Register Use Type Program Models Interrupt LatencyTMS320C54xx Rules and Guidelines TMS320C54xx Rules and Guidelines ST1 Field Name Use Type Status RegistersST0 Field Name Use Type Pmst Field Name Use Type TMS320C55x Rules and GuidelinesStack Architecture Example Relocatability SSP ST3 Field Name Use Type Status BitsST2 Field Name Use Type Homy General TMS320C24xx Guidelines TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA Resource Algorithm and Framework Overview Logical Channel Requirements for the Use of the DMA Resource Data Transfer Synchronization Data Transfer Properties DMA Rule Abstract InterfaceDMA Guideline Average Maximum Resource CharacterizationData Transfers bytes Frequency Strong Ordering of DMA Transfer Requests Runtime APIs Device Independent DMA Optimization Guideline Submitting DMA Transfer Requests 13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers 14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers Non-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm Synchronization Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization Rules General Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library DSP/BIOS Run-time Support Library Books Bibliography Submit Documentation Feedback Glossary of Terms Glossary Glossary of Terms Glossary of Terms Important Notice