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TMS320C55x Rules and Guidelines

ST1 Field Name

Use

Type

INTM

Interrupt mask

Preserve(global)

OVM

Overflow mode bit

Preserve (local)

SXM

Fractional mode bit

Scratch (local)

XF

External Flag

Scratch (global)

The PMST register is used to control the processor mode and is of type Init.

PMST Field Name

Use

Type

AVIS

Address Visibility bit

Read-only (global)

CLKOFF

CLKOUT disable bit

Read-only (global)

DROM

Map ROM into data space

Read-only (local)

IPTR

Interrupt Vector Table Pointer

Read-only (global)

MP/MC

Microprocessor/microcomputer mode bit

Read-only (global)

OVLY

RAM Overlay bit

Read-only (local)

SMUL

Saturation on multiply bit

Init (local)

SST

Saturation on store

Init (local)

5.4.5 Interrupt Latency

Although there are no additional rules for C54x algorithms that deal with interrupt latency, it is important to note that all RPT and RPTZ loops are non-interruptible; i.e., once started, interrupts are blocked until the entire loop completes. Thus, the length of these loops can have a significant effect on the worst case interrupt latency of an algorithm.

5.5TMS320C55x Rules and Guidelines

This section describes the rules and guidelines that are specific to the TMS320C5500 family of DSPs.

5.5.1 Stack Architecture

The C55X CPU supports different stack configurations and the stack configuration register (4 bits) selects the stack architecture. The selection of the stack architecture can be done only on a hardware or software reset. To facilitate integration, each algorithm must publish the stack configuration that it uses.

Rule 31

All C55x algorithms must document the content of the stack configuration register that they follow.

Guideline 14

All C55x algorithms should not assume any specific stack configuration and should work under all the three stack modes.

5.5.2 Data Models

The C55X compiler supports a small memory model and a large memory model. These memory models affect how data is placed in memory and accessed. The use of a small memory model results in code and data sizes that are slightly smaller than when using the large memory model. However, this imposes certain constraints on the size and memory placement. In the small memory model, the total size of the directly accessed data in an application must all fit within a single page of memory that is 64K words in size. Since algorithms are agnostic of where they are going to be instanced; all global and static data references should be far references.

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DSP-Specific Guidelines

SPRU352G –June 2005 –Revised February 2007

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Texas Instruments TMS320 DSP manual TMS320C55x Rules and Guidelines, Stack Architecture, Pmst Field Name Use Type