Status Bits, ST2 Field Name Use Type | Texas Instruments TMS320 DSP

www.ti.com

TMS320C55x Rules and Guidelines

5.5.6 Status Bits

The C55xx contains four status registers: ST0, ST1, ST2 and ST3.

ST0 Field Name	Use	Type
ACOV2	Overflow flag for AC2	Scratch (local)
ACOV3	Overflow flag for AC3	Scratch (local)
TC1, TC2	Test control flag	Scratch (local)
C	Carry bit	Scratch (local)
ACOV0	Overflow flag for AC0	Scratch (local)
ACOV1	Overflow flag for AC1	Scratch (local)
DP bits (15 to 7)	Data page pointer	Scratch (local)

The following table gives the attributes for the ST1 register fields.

ST1 Field Name	Use	Type
BRAF	Block repeat active flag	Preserve (local)
CPL=1	Compiler mode bit	Init (local)
XF	External flag	Scratch (local)
HM	Host mode bit	Preserve (local)
INTM	Interrupt Mask	Preserve (global)
M40 = 0	40/32-bit computation control for the D-unit	Init (local)
SATD = 0	Saturation control for D-unit	Init (local)
SXMD = 1	Sign extension mode bit for D-unit	Init (local)
C16 = 0	Dual 16-bit math bit	Init (local)
FRCT = 0	Fractional mode bit	Init (local)
LEAD = 0	Lead bit	Init (local)
T2 bits (0 to 4)	Accumulator shift mode	Scratch (local)

The following table describes the attributes for the ST2 register.

ST2 Field Name	Use	Type
ARMS=0	AR Modifier Switch	Init (local)
XCNA	Conditional Execute Control - Address	Read-only (local)
XCND	Conditional Execute Control - Data	Read-only (local)
DBGM	Debug enable mask bit	Read-only (global)
EALLOW	Emulation access enable bit	Read-only (global)
RDM=0	Rounding Mode	Init (local)
CDPLC	Linear/Circular configuration for the CDP pointer	Preserve (local)
AR7LC to AR0LC	Linear/Circular configuration for the AR7 to AR0	Preserve (local)
	pointer

The following table describes the attributes for the ST3 register.

ST3 Field Name	Use	Type
CAFRZ	Cache Freeze	Read-only (global)
CAEN	Cache Enable	Read-only (global)
CACLR	Cache Clear	Read-only (global)
HINT	Host Interrupt	Read-only (global)
SPRU352G –June 2005 –Revised February 2007		DSP-Specific Guidelines	55
Submit Documentation Feedback

Image 55

Texas Instruments TMS320 DSP manual Status Bits, ST2 Field Name Use Type, ST3 Field Name Use Type

Contents

Rules and Guidelines Users Guide Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Guideline n Related DocumentationText Conventions Rule n Overview Rules for TMS320C5x Rules for TMS320C6x Scope of the Standard Requirements of the Standard Rules and Guidelines Intentional Omissions Goals of the Standard Frameworks System Architecture Core Run-Time Support Algorithms General Programming Guidelines Rule Use of C LanguageThreads and Reentrancy Threads Reentrancy Preemptive vs. Non-Preemptive Multitasking Example Data Memory Data Memory Scratch versus Persistent Memory Spaces Scratch vs Persistent Memory Allocation Guideline Algorithm versus Application ROM-ability Program MemorySection Name Purpose Use of Peripherals Use of Peripherals Interfaces and Modules Algorithms Packaging Algorithm Component Model Implementation Fir.h Interfaces and Modules External Identifiers Module Initialization and Finalization Naming ConventionsModule Instance Objects Run-Time Object Creation and Deletion Design-Time Object Creation Example Module Module Configuration Multiple Interface Support Description Required Interface InheritanceSummary Element Algorithms Algorithms Object Code Packaging Debug Verses Release Header Files Moduleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance Characterization External Heap MemorySize Static Local and Global Data Memory Stack Memory Data Bss Object files Size Operation Interrupt LatencyExecution Time Mips Is Not Enough Execution Timeline for Two Periodic Tasks Execution Time Model 198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register Types Data Models Use of Floating PointTMS320C6xxx Rules and Guidelines Endian Byte Ordering CSR Field Use Type Register ConventionsStatus Register Register Use Type TMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Example Relocatability SSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy General TMS320C24xx Guidelines TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA Resource Algorithm and Framework Overview Logical Channel Requirements for the Use of the DMA Resource Data Transfer Synchronization Data Transfer Properties DMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIs Device Independent DMA Optimization Guideline Submitting DMA Transfer Requests 13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers 14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers Non-Preemptive System Minimizing Logical Channel Reconfiguration OverheadAddressing Automatic Endianism Conversion Issues Inter-Algorithm Synchronization Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization Rules General Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library DSP/BIOS Run-time Support Library Books Bibliography Submit Documentation Feedback Glossary of Terms Glossary Glossary of Terms Glossary of Terms Important Notice