Use of the DMA Resource | Texas Instruments TMS320 DSP instruction

Chapter 6

SPRU352G – June 2005 – Revised February 2007

Use of the DMA Resource

The direct memory access (DMA) controller performs asynchronously scheduled data transfers in the background while the CPU continues to execute instructions. In this chapter, we develop additional rules and guidelines for creating eXpressDSP-compliant algorithms that utilize the DMA resources.

Topic		Page
6.1	Overview	62
6.2	Algorithm and Framework	62
6.3	Requirements for the Use of the DMA Resource	63
6.4	Logical Channel	63
6.5	Data Transfer Properties	64
6.6	Data Transfer Synchronization	64
6.7	Abstract Interface	65
6.8	Resource Characterization	66
6.9	Runtime APIs	67
6.10	Strong Ordering of DMA Transfer Requests	67
6.11	Submitting DMA Transfer Requests	68
6.12	Device Independent DMA Optimization Guideline	68
6.13	C6xxx Specific DMA Rules and Guidelines	69
6.14	C55x Specific DMA Rules and Guidelines	70
6.15	Inter-Algorithm Synchronization	71

SPRU352G –June 2005 –Revised February 2007

Use of the DMA Resource

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Texas Instruments TMS320 DSP manual Use of the DMA Resource, Submitting DMA Transfer Requests

Contents

Rules and Guidelines Users Guide Submit Documentation Feedback Contents Use of the DMA Resource Urls List of Figures Intended Audience Read This FirstDocument Overview Text Conventions Related DocumentationRule n Guideline n Overview Rules for TMS320C5x Rules for TMS320C6x Scope of the Standard Requirements of the Standard Rules and Guidelines Intentional Omissions Goals of the Standard Frameworks System Architecture Core Run-Time Support Algorithms General Programming Guidelines Threads and Reentrancy Use of C LanguageThreads Rule Reentrancy Preemptive vs. Non-Preemptive Multitasking Example Data Memory Data Memory Scratch versus Persistent Memory Spaces Scratch vs Persistent Memory Allocation Guideline Algorithm versus Application ROM-ability Program MemorySection Name Purpose Use of Peripherals Use of Peripherals Interfaces and Modules Algorithms Packaging Algorithm Component Model Implementation Fir.h Interfaces and Modules External Identifiers Module Initialization and Finalization Naming ConventionsModule Instance Objects Run-Time Object Creation and Deletion Design-Time Object Creation Example Module Module Configuration Multiple Interface Support Summary Interface InheritanceElement Description Required Algorithms Algorithms Object Code Packaging Debug Verses Release Header Files Moduleversvendorvariant.1arch Data Memory Program Memory Interrupt Latency Execution Time Algorithm Performance Characterization External Heap MemorySize Static Local and Global Data Memory Stack Memory Data Bss Object files Size Execution Time Interrupt LatencyMips Is Not Enough Operation Execution Timeline for Two Periodic Tasks Execution Time Model 198000 Process59000 198000 Submit Documentation Feedback DSP-Specific Guidelines Register Types CPU Register Types TMS320C6xxx Rules and Guidelines Use of Floating PointEndian Byte Ordering Data Models Status Register Register ConventionsRegister Use Type CSR Field Use Type TMS320C54xx Rules and Guidelines Interrupt LatencyProgram Models TMS320C54xx Rules and Guidelines ST0 Field Name Use Type Status RegistersST1 Field Name Use Type Stack Architecture TMS320C55x Rules and GuidelinesPmst Field Name Use Type Example Relocatability SSP ST2 Field Name Use Type Status BitsST3 Field Name Use Type Homy General TMS320C24xx Guidelines TMS320C28x Rules and Guidelines TMS320C28x Rules and Guidelines XAR0 M0M1MAP Submitting DMA Transfer Requests Use of the DMA Resource Algorithm and Framework Overview Logical Channel Requirements for the Use of the DMA Resource Data Transfer Synchronization Data Transfer Properties DMA Guideline Abstract InterfaceDMA Rule Data Transfers bytes Frequency Resource CharacterizationAverage Maximum Strong Ordering of DMA Transfer Requests Runtime APIs Device Independent DMA Optimization Guideline Submitting DMA Transfer Requests 13 C6xxx Specific DMA Rules and Guidelines Cache Coherency Issues for Algorithm Producers 14 C55x Specific DMA Rules and Guidelines Supporting Packed/Burst Mode DMA Transfers Addressing Automatic Endianism Conversion Issues Minimizing Logical Channel Reconfiguration OverheadInter-Algorithm Synchronization Non-Preemptive System Preemptive System Algorithm B Algorithm a Inter-Algorithm Synchronization Appendix a General Rules DMA Rules Performance Characterization Rules General Guidelines DMA Guidelines Submit Documentation Feedback Core Run-Time APIs DSP/BIOS Run-time Support Library TI C-Language Run-Time Support Library DSP/BIOS Run-time Support Library Books Bibliography Submit Documentation Feedback Glossary of Terms Glossary Glossary of Terms Glossary of Terms Important Notice