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Texas Instruments TMS320DM643 manual Write WRT Command, DDR2 WRT Command

Models: TMS320DM643

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2.4.5Write (WRT) Command

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Peripheral Architecture

2.4.5Write (WRT) Command

Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed.

Figure 9 shows the timing for a write on the DDR2 memory controller.

If the transfer request is for less than 8 words, depending on the scheduling result and the pending commands, the DDR2 memory controller can:

∙Mask out the additional data using DDR_DQM outputs

∙Terminate the write burst and start a new write burst

The DDR2 memory controller does not perform the DEAC command until page information becomes invalid.

Figure 9. DDR2 WRT Command

DDR_CLK

DDR_CLK

Sample

Write Latency

DDR_CKE

DDR_CS

DDR_RAS

DDR_CAS

DDR_WE

DDR_A[12:0] COL

DDR_BA[2:0] BANK

DDR_A[10]

DDR_DQM[3:0] DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8

DDR_D[31:0]

D0

D1

D2

D3

D4

D5

D6

D7

DDR_DQS[3:0]

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DDR2 Memory Controller

SPRU986B–November 2007

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Texas Instruments TMS320DM643 manual Write WRT Command, DDR2 WRT Command

Contents

Users Guide TMS320DM643x DMP DDR2 Memory ControllerSPRU986B-November Submit Documentation FeedbackContents List of Figures List of FiguresList of Tables About This Manual Read This FirstPreface Notational Conventions1.2 Features DDR2 Memory ControllerUsers Guide 1 Introduction1.5 Industry Standards Compliance Statement 1.3 Functional Block Diagram1.4 Supported Use Case Statement Figure 1. Data Paths to DDR2 Memory Controller2.1 Clock Control Figure 2. DDR2 Memory Controller Clock Block Diagram2 Peripheral Architecture 2.1.1 Clock Source2.2 Memory Map 2.1.2 Clock ConfigurationTable 1. PLLC2 Configuration 2.1.3 DDR2 Memory Controller Internal Clock DomainsTable 2. DDR2 Memory Controller Signal Descriptions 2.3 Signal DescriptionsFigure 3. DDR2 Memory Controller Signals Peripheral Architecture2.4 Protocol Descriptions Table 3. DDR2 SDRAM CommandsTable 4. Truth Table for DDR2 SDRAM Commands Peripheral ArchitectureDDRCLK DDRCLK 2.4.1 Refresh ModeFigure 4. Refresh Command DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10 Figure 5. DCAB Command2.4.2 Deactivation DCAB and DEAC DDRBA20 DDRDQM30DDR2 Memory Controller Figure 6. DEAC CommandPeripheral Architecture Submit Documentation FeedbackFigure 7. ACTV Command 2.4.3 Activation ACTVDDRA120 DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL 2.4.4 READ CommandFigure 8. DDR2 READ Command DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency2.4.5 Write WRT Command Figure 9. DDR2 WRT Command2.4.6 Mode Register Set MRS and EMRS Figure 10. DDR2 MRS and EMRS Command2.5 Memory Width and Byte Alignment Table 5. Addressable Memory RangesFigure 11. Byte Alignment 2.6 Endianness Considerations Table 6. 16-Bit External MemoryTable 7. 32-Bit External Memory Table 8. Bank Configuration Register Fields for Address Mapping 2.7 Address MappingPeripheral Architecture Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM DDR2 Memory ControllerFigure 12. Logical Address-to-DDR2 SDRAM Address Map Peripheral ArchitectureDDR2 Memory Controller Figure 13. DDR2 SDRAM Column, Row, and Bank AccessPeripheral Architecture Submit Documentation FeedbackFigure 14. DDR2 Memory Controller FIFO Block Diagram 2.8 DDR2 Memory Controller InterfaceTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.2 Command Starvation 2.8.3 Possible Race Condition2.10 Self-Refresh Mode 2.9 Refresh SchedulingTable 12. Refresh Urgency Levels 2.11 Reset Considerations Table 13. Reset SourcesFigure 15. DDR2 Memory Controller Reset Block Diagram 2.12 VTP IO Buffer Calibration 2.13 Auto-Initialization Sequence2.13.1 Initializing Configuration Registers Table 14. DDR2 SDRAM Configuration by MRS CommandTable 15. DDR2 SDRAM Configuration by EMRS1 Command Write recovery from autoprecharge. Value of2.13.2 Initializing Following Device Power Up and Device RESET 2.14 Interrupt Support 2.16 Power ManagementFigure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.15 DMA Event Support2.16.1 DDR2 Memory Controller Clock Stop Procedure 2.17 Emulation Considerations3.1 Connecting the DDR2 Memory Controller to DDR2 Memory 3 Supported Use CasesSupported Use Cases Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection 200 Ω 200 Ω3.2.2 Configuring SDRAM Refresh Control Register SDRCR 3.2.1 Configuring SDRAM Bank Configuration Register SDBCRTable 16. SDRAM Bank Configuration Register SDBCR Configuration Table 17. DDR2 Memory Refresh Specification3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2 Table 19. SDRAM Timing Register SDTIMR ConfigurationTable 20. SDRAM Timing Register 2 SDTIMR2 Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCR Table 21. DDR PHY Control Register DDRPHYCR Configuration4 DDR2 Memory Controller Registers 4.1 SDRAM Status Register SDRSTAT Figure 19. SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions Table 26. SDRAM Bank Configuration Register SDBCR Field Descriptions 4.2 SDRAM Bank Configuration Register SDBCRFigure 20. SDRAM Bank Configuration Register SDBCR DDR2 Memory Controller RegistersDDR2 Memory Controller Registers DDR2 Memory ControllerSubmit Documentation Feedback Table 27. SDRAM Refresh Control Register SDRCR Field Descriptions 4.3 SDRAM Refresh Control Register SDRCRFigure 21. SDRAM Refresh Control Register SDRCR DDR2 Memory Controller RegistersTable 28. SDRAM Timing Register SDTIMR Field Descriptions 4.4 SDRAM Timing Register SDTIMRFigure 22. SDRAM Timing Register SDTIMR DDR2 Memory Controller RegistersTable 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions 4.5 SDRAM Timing Register 2 SDTIMR2Figure 23. SDRAM Timing Register 2 SDTIMR2 DDR2 Memory Controller Registers4.6 Peripheral Bus Burst Priority Register PBBPR Figure 24. Peripheral Bus Burst Priority Register PBBPRTable 31. Interrupt Raw Register IRR Field Descriptions 4.7 Interrupt Raw Register IRRFigure 25. Interrupt Raw Register IRR DDR2 Memory Controller Registers4.8 Interrupt Masked Register IMR Figure 26. Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions Table 33. Interrupt Mask Set Register IMSR Field Descriptions 4.9 Interrupt Mask Set Register IMSRFigure 27. Interrupt Mask Set Register IMSR DDR2 Memory Controller RegistersTable 34. Interrupt Mask Clear Register IMCR Field Descriptions 4.10 Interrupt Mask Clear Register IMCRFigure 28. Interrupt Mask Clear Register IMCR DDR2 Memory Controller RegistersTable 35. DDR PHY Control Register DDRPHYCR Field Descriptions 4.11 DDR PHY Control Register DDRPHYCRFigure 29. DDR PHY Control Register DDRPHYCR DDR2 Memory Controller RegistersTable 36. VTP IO Control Register VTPIOCR Field Descriptions 4.12 VTP IO Control Register VTPIOCRFigure 30. VTP IO Control Register VTPIOCR DDR2 Memory Controller RegistersTable 38. DDR VTP Enable Register DDRVTPER Field Descriptions 4.14 DDR VTP Enable Register DDRVTPERFigure 32. DDR VTP Enable Register DDRVTPER 4.13 DDR VTP Register DDRVTPRAppendix A Appendix A Revision HistoryTable A-1. Document Revision History SectionProducts power.ti.comIMPORTANT NOTICE Applications