Contents | Texas Instruments TMS320DM643 specs

Contents


Preface				6
1	Introduction			7
	1.1	Purpose of the Peripheral		7
	1.2	Features		7
	1.3	Functional Block Diagram		8
	1.4	Supported Use Case Statement		8
	1.5	Industry Standard(s) Compliance Statement		8
2	Peripheral Architecture			9
	2.1	Clock Control		9
	2.2	Memory Map		10
	2.3	Signal Descriptions		11
	2.4	Protocol Description(s)		12
	2.5	Memory Width and Byte Alignment		20
	2.6	Endianness Considerations		21
	2.7	Address Mapping		22
	2.8	DDR2 Memory Controller Interface		26
	2.9	Refresh Scheduling		29
	2.10	Self-Refresh Mode		29
	2.11	Reset Considerations		30
	2.12	VTP IO Buffer Calibration		31
	2.13	Auto-Initialization Sequence		31
	2.14	Interrupt Support		34
	2.15	DMA Event Support		34
	2.16	Power Management		34
	2.17	Emulation Considerations		35
3	Supported Use Cases			36
	3.1	Connecting the DDR2 Memory Controller to DDR2 Memory		36
	3.2	Configuring Memory-Mapped Registers to Meet DDR2-400 Specification		36
4	DDR2 Memory Controller Registers			40
	4.1	SDRAM Status Register (SDRSTAT)		41
	4.2	SDRAM Bank Configuration Register (SDBCR)		42
	4.3	SDRAM Refresh Control Register (SDRCR)		44
	4.4	SDRAM Timing Register (SDTIMR)		45
	4.5	SDRAM Timing Register 2 (SDTIMR2)		46
	4.6	Peripheral Bus Burst Priority Register (PBBPR)		47
	4.7	Interrupt Raw Register (IRR)		48
	4.8	Interrupt Masked Register (IMR)		49
	4.9	Interrupt Mask Set Register (IMSR)		50
	4.10	Interrupt Mask Clear Register (IMCR)		51
	4.11	DDR PHY Control Register (DDRPHYCR)		52
	4.12	VTP IO Control Register (VTPIOCR)		53
	4.13	DDR VTP Register (DDRVTPR)		54
	4.14	DDR VTP Enable Register (DDRVTPER)		54
Appendix A		Revision History		55
SPRU986B–November 2007			Table of Contents	3

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Texas Instruments TMS320DM643 manual Contents

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral Features Functional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock Control 3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory Map Pin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active high Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function Refresh Command Refresh Mode Deactivation Dcab and Deac Dcab Command Deac Command Activation Actv Actv Command DDR2 Read Command Read Command DDR2 WRT Command Write WRT Command DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Addressable Memory Ranges Memory Width and Byte Alignment Internal Data 64-Bit DDRA2 DDRD310 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA21 DDRD150 Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept Possible Race Condition Command Starvation Urgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency Levels Reset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer Calibration DDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration Registers Peripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 Memory Connecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register Sdrcr DDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 Configuration D63-32 Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration Register Field Name Description DDR VTP Register Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Acronym Register Description Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register Sdrcr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2 Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRR Interrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMR Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register Imcr DDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register Ddrphycr VTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register Vtpiocr DDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Additions/Modifications/Deletions Table A-1. Document Revision History Important Notice