Texas Instruments TMS320DM643 manual Command Ordering and Scheduling, Advanced Concept

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Peripheral Architecture

2.8.1Command Ordering and Scheduling, Advanced Concept

The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address, and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. Command re-ordering takes place within the command FIFO.

Typically, a given master issues commands on a single priority. EDMA transfer controller read and write ports are different masters. The DDR2 memory controller first reorders commands from each master based on the following rules:

∙Selects the oldest command (first command in the queue)

∙Selects a read before a write if:

–The read is to a different block address (2048 bytes) than the write

–The read has greater or equal priority

The second bullet above may be viewed as an exception to the first bullet. This means that for an individual master, all of its commands will complete from oldest to newest, with the exception that a read may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master may have one command ready for execution.

Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering:

∙Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open.

∙Selects the highest priority command from pending reads and writes to open rows. If multiple commands have the highest priority, then the DDR2 memory controller selects the oldest command.

The DDR2 memory controller may now have a final read and write command. If the Read FIFO is not full, then the read command will be performed before the write command, otherwise the write command will be performed first.

Besides commands received from on-chip resources, the DDR2 memory controller also issues refresh commands. The DDR2 memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2 memory controller issues read, write, and refresh commands to DDR2 SDRAM memory, it adheres to the following rules:

1.Refresh request resulting from the Refresh Must level of urgency being reached

2.Read request without a higher priority write (selected from above reordering algorithm)

3.Refresh request resulting from the Refresh Need level of urgency being reached

4.Write request (selected from above reordering algorithm)

5.Refresh request resulting from Refresh May level of urgency being reached

6.Request to enter self-refresh mode

The following results from the above scheduling algorithm:

∙All writes from a single master will complete in order

∙All reads from a single master will complete in order

∙From the same master, any read to the same location (or within 2048 bytes) as a previous write will complete in order

SPRU986B–November 2007 DDR2 Memory Controller 27

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