DDR PHY Control Register Ddrphycr | Texas Instruments TMS320DM643

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DDR2 Memory Controller Registers

4.11 DDR PHY Control Register (DDRPHYCR)

The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operation and determines whether the DLL is in reset, whether it is powered up, and the read latency. The DDRPHYCR is shown in Figure 29 and described in Table 35.

Figure 29. DDR PHY Control Register (DDRPHYCR)

31						16
	Reserved
	R/W-5000h
15	6	5	4	3	2	0
Reserved		DLLRESET	DLLPWRDN	Rsvd		READLAT
R/W-190h		R/W-0	R/W-1	R-1		R/W-7h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 35. DDR PHY Control Register (DDRPHYCR) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	5000h	Reserved. Always write 5000h to these bits.
15-6	Reserved	190h	Reserved. Always write 190h to these bits.
5	DLLRESET		Reset DLL.
		0	DLL is out of reset.
		1	Places the DLL in reset.
4	DLLPWRDN		Power down DLL.
		0	DLL is powered up.
		1	DLL is powered down, if DLLPWRDN and the SR bit and MCLKSTOPEN bit in the SDRAM
			refresh control register (SDRCR) are set to 1.
3	Reserved	1	Reserved
2-0	READLAT	0-7h	Read latency. Read latency is equal to CAS latency plus round trip board delay for data
			minus 1. The maximum value of read latency that is supported is CAS latency plus 3. The
			minimum read latency value that is supported is CAS latency plus 1. The read latency value
			is defined in number of MCLK/DDR_CLK cycles.

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DDR2 Memory Controller

SPRU986B–November 2007

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Texas Instruments TMS320DM643 manual DDR PHY Control Register Ddrphycr Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Supported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock Source Clock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains Signal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Endianness Considerations Bit External MemoryInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310 Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Self-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization Sequence DDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Configuring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula Configuring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D63-32 Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsAcronym Register Description DDR VTP Register Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice