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Texas Instruments TMS320DM643 SDRAM Timing Register 2 SDTIMR2, DDR2 Memory Controller Registers

Models: TMS320DM643

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4.5SDRAM Timing Register 2 (SDTIMR2)

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DDR2 Memory Controller Registers

4.5SDRAM Timing Register 2 (SDTIMR2)

Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. See the DDR2 data sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 23 and described in Table 29.

Figure 23. SDRAM Timing Register 2 (SDTIMR2)

31	25	24	23	22		16
Reserved		Reserved				T_XSNR
R-0			R/W-x			R/W-1Dh
15		8	7	5	4	0
T_XSRD				T_RTP		T_CKE
R/W-F1h				R/W-2h		R/W-5h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset; -x = value is indeterminate after reset

Table 29. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions

Bit	Field	Value	Description
31-25	Reserved	0	Reserved
24-23	Reserved	x	Reserved. Reset value is indeterminate.
22-16	T_XSNR	0-7Fh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to any other command
			except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2 data
			sheet. Calculate by:
			T_XSNR = (txsnr/DDR_CLK period) - 1
15-8	T_XSRD	0-FFh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to a read command,
			minus 1. Corresponds to the txsrd AC timing parameter in the DDR2 data sheet. Calculate by:
			T_XSRD = txsrd - 1
7-5	T_RTP	0-7h	Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
			command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2 data sheet. Calculate by:
			T_RTP = (trtp/DDR_CLK period) - 1
4-0	T_CKE	0-1Fh	Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
			Corresponds to the tcke AC timing parameter in the DDR2 data sheet. Calculate by:

T_CKE = tcke - 1

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DDR2 Memory Controller

SPRU986B–November 2007

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Texas Instruments TMS320DM643 SDRAM Timing Register 2 SDTIMR2 Field Descriptions, DDR2 Memory Controller Registers

Contents

Users Guide TMS320DM643x DMP DDR2 Memory ControllerSPRU986B-November Submit Documentation FeedbackContents List of Figures List of FiguresList of Tables About This Manual Read This FirstPreface Notational Conventions1.2 Features DDR2 Memory ControllerUsers Guide 1 Introduction1.5 Industry Standards Compliance Statement 1.3 Functional Block Diagram1.4 Supported Use Case Statement Figure 1. Data Paths to DDR2 Memory Controller2.1 Clock Control Figure 2. DDR2 Memory Controller Clock Block Diagram2 Peripheral Architecture 2.1.1 Clock Source2.2 Memory Map 2.1.2 Clock ConfigurationTable 1. PLLC2 Configuration 2.1.3 DDR2 Memory Controller Internal Clock DomainsTable 2. DDR2 Memory Controller Signal Descriptions 2.3 Signal DescriptionsFigure 3. DDR2 Memory Controller Signals Peripheral Architecture2.4 Protocol Descriptions Table 3. DDR2 SDRAM CommandsTable 4. Truth Table for DDR2 SDRAM Commands Peripheral ArchitectureDDRCLK DDRCLK 2.4.1 Refresh ModeFigure 4. Refresh Command DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10 Figure 5. DCAB Command2.4.2 Deactivation DCAB and DEAC DDRBA20 DDRDQM30DDR2 Memory Controller Figure 6. DEAC CommandPeripheral Architecture Submit Documentation Feedback2.4.3 Activation ACTV Figure 7. ACTV CommandDDRA120 DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL 2.4.4 READ CommandFigure 8. DDR2 READ Command DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency2.4.5 Write WRT Command Figure 9. DDR2 WRT Command2.4.6 Mode Register Set MRS and EMRS Figure 10. DDR2 MRS and EMRS CommandTable 5. Addressable Memory Ranges 2.5 Memory Width and Byte AlignmentFigure 11. Byte Alignment Table 6. 16-Bit External Memory 2.6 Endianness ConsiderationsTable 7. 32-Bit External Memory Table 8. Bank Configuration Register Fields for Address Mapping 2.7 Address MappingPeripheral Architecture Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM DDR2 Memory ControllerFigure 12. Logical Address-to-DDR2 SDRAM Address Map Peripheral ArchitectureDDR2 Memory Controller Figure 13. DDR2 SDRAM Column, Row, and Bank AccessPeripheral Architecture Submit Documentation Feedback2.8 DDR2 Memory Controller Interface Figure 14. DDR2 Memory Controller FIFO Block DiagramTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.2 Command Starvation 2.8.3 Possible Race Condition2.9 Refresh Scheduling 2.10 Self-Refresh ModeTable 12. Refresh Urgency Levels Table 13. Reset Sources 2.11 Reset ConsiderationsFigure 15. DDR2 Memory Controller Reset Block Diagram 2.12 VTP IO Buffer Calibration 2.13 Auto-Initialization Sequence2.13.1 Initializing Configuration Registers Table 14. DDR2 SDRAM Configuration by MRS CommandTable 15. DDR2 SDRAM Configuration by EMRS1 Command Write recovery from autoprecharge. Value of2.13.2 Initializing Following Device Power Up and Device RESET 2.14 Interrupt Support 2.16 Power ManagementFigure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.15 DMA Event Support2.16.1 DDR2 Memory Controller Clock Stop Procedure 2.17 Emulation Considerations3.1 Connecting the DDR2 Memory Controller to DDR2 Memory 3 Supported Use CasesSupported Use Cases Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection 200 Ω 200 Ω3.2.2 Configuring SDRAM Refresh Control Register SDRCR 3.2.1 Configuring SDRAM Bank Configuration Register SDBCRTable 16. SDRAM Bank Configuration Register SDBCR Configuration Table 17. DDR2 Memory Refresh SpecificationTable 19. SDRAM Timing Register SDTIMR Configuration 3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2Table 20. SDRAM Timing Register 2 SDTIMR2 Configuration Table 21. DDR PHY Control Register DDRPHYCR Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCR4 DDR2 Memory Controller Registers Figure 19. SDRAM Status Register SDRSTAT 4.1 SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions Table 26. SDRAM Bank Configuration Register SDBCR Field Descriptions 4.2 SDRAM Bank Configuration Register SDBCRFigure 20. SDRAM Bank Configuration Register SDBCR DDR2 Memory Controller RegistersDDR2 Memory Controller DDR2 Memory Controller RegistersSubmit Documentation Feedback Table 27. SDRAM Refresh Control Register SDRCR Field Descriptions 4.3 SDRAM Refresh Control Register SDRCRFigure 21. SDRAM Refresh Control Register SDRCR DDR2 Memory Controller RegistersTable 28. SDRAM Timing Register SDTIMR Field Descriptions 4.4 SDRAM Timing Register SDTIMRFigure 22. SDRAM Timing Register SDTIMR DDR2 Memory Controller RegistersTable 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions 4.5 SDRAM Timing Register 2 SDTIMR2Figure 23. SDRAM Timing Register 2 SDTIMR2 DDR2 Memory Controller Registers4.6 Peripheral Bus Burst Priority Register PBBPR Figure 24. Peripheral Bus Burst Priority Register PBBPRTable 31. Interrupt Raw Register IRR Field Descriptions 4.7 Interrupt Raw Register IRRFigure 25. Interrupt Raw Register IRR DDR2 Memory Controller RegistersFigure 26. Interrupt Masked Register IMR 4.8 Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions Table 33. Interrupt Mask Set Register IMSR Field Descriptions 4.9 Interrupt Mask Set Register IMSRFigure 27. Interrupt Mask Set Register IMSR DDR2 Memory Controller RegistersTable 34. Interrupt Mask Clear Register IMCR Field Descriptions 4.10 Interrupt Mask Clear Register IMCRFigure 28. Interrupt Mask Clear Register IMCR DDR2 Memory Controller RegistersTable 35. DDR PHY Control Register DDRPHYCR Field Descriptions 4.11 DDR PHY Control Register DDRPHYCRFigure 29. DDR PHY Control Register DDRPHYCR DDR2 Memory Controller RegistersTable 36. VTP IO Control Register VTPIOCR Field Descriptions 4.12 VTP IO Control Register VTPIOCRFigure 30. VTP IO Control Register VTPIOCR DDR2 Memory Controller RegistersTable 38. DDR VTP Enable Register DDRVTPER Field Descriptions 4.14 DDR VTP Enable Register DDRVTPERFigure 32. DDR VTP Enable Register DDRVTPER 4.13 DDR VTP Register DDRVTPRAppendix A Appendix A Revision HistoryTable A-1. Document Revision History SectionProducts power.ti.comIMPORTANT NOTICE Applications