Sdram Timing Register 2 SDTIMR2 | Texas Instruments TMS320DM643

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DDR2 Memory Controller Registers

4.5SDRAM Timing Register 2 (SDTIMR2)

Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 register is programmable only when the TIMUNLOCK bit is set to 1 in the SDBCR. See the DDR2 data sheet for information on the appropriate values to program each field. SDTIMR2 is shown in Figure 23 and described in Table 29.

Figure 23. SDRAM Timing Register 2 (SDTIMR2)

31	25	24	23	22		16
Reserved		Reserved				T_XSNR
R-0			R/W-x			R/W-1Dh
15		8	7	5	4	0
T_XSRD				T_RTP		T_CKE
R/W-F1h				R/W-2h		R/W-5h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset; -x = value is indeterminate after reset

Table 29. SDRAM Timing Register 2 (SDTIMR2) Field Descriptions

Bit	Field	Value	Description
31-25	Reserved	0	Reserved
24-23	Reserved	x	Reserved. Reset value is indeterminate.
22-16	T_XSNR	0-7Fh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to any other command
			except a read command, minus 1. Corresponds to the txsnr AC timing parameter in the DDR2 data
			sheet. Calculate by:
			T_XSNR = (txsnr/DDR_CLK period) - 1
15-8	T_XSRD	0-FFh	Specifies the minimum number of DDR_CLK cycles from a self-refresh exit to a read command,
			minus 1. Corresponds to the txsrd AC timing parameter in the DDR2 data sheet. Calculate by:
			T_XSRD = txsrd - 1
7-5	T_RTP	0-7h	Specifies the minimum number of DDR_CLK cycles from a last read command to a precharge
			command, minus 1. Corresponds to the trtp AC timing parameter in the DDR2 data sheet. Calculate by:
			T_RTP = (trtp/DDR_CLK period) - 1
4-0	T_CKE	0-1Fh	Specifies the minimum number of DDR_CLK cycles between transitions on the DDR_CKE pin, minus 1.
			Corresponds to the tcke AC timing parameter in the DDR2 data sheet. Calculate by:

T_CKE = tcke - 1

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DDR2 Memory Controller

SPRU986B–November 2007

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Texas Instruments TMS320DM643 manual Sdram Timing Register 2 SDTIMR2 Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Supported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock Source Memory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock Domains Clock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type Description Command Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Internal Data 64-Bit DDRA21 DDRD150 Endianness ConsiderationsBit External Memory Internal Data 64-Bit DDRA2 DDRD310 Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Refresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level Description Reset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization Sequence Initializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory Controller Peripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh Specification Sdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual Formula Register Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration D63-32 Acronym Register Description Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions DDR VTP Register Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice