Functional Block Diagram | Texas Instruments TMS320DM643 specs

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Introduction

1.3Functional Block Diagram

The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays the general data paths to on-chip peripherals and external DDR2 SDRAM.

Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controller through the switched central resource (SCR).

Figure 1. Data Paths to DDR2 Memory Controller

DSP

Master peripherals

EDMA VPSS

SCR

BUS

DDR2

memory controller

External

BUS DDR2 SDRAM

1.4Supported Use Case Statement

The DDR2 memory controller supports JESD79D-2A DDR2-400 SDRAM memories utilizing either 32-bit or 16-bit of the DDR2 memory controller data bus. See Section 3 for more details.

1.5Industry Standard(s) Compliance Statement

The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the exception of the following feature list:

∙On Die Termination (ODT). The DDR2 memory controller does not include any on-die terminating resistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled by tying the ODT input pin of the DDR2 SDRAM to ground.

∙Differential DQS. The DDR2 memory controller supports single ended DQS signals.

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DDR2 Memory Controller

SPRU986B–November 2007

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Texas Instruments TMS320DM643 manual Functional Block Diagram, Supported Use Case Statement

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Control Clock Source Clock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains Signal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Endianness Considerations Bit External MemoryInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310 Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Self-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Signal Reset Source Reset ConsiderationsReset Sources VTP IO Buffer Calibration Auto-Initialization Sequence DDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Configuring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula Configuring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D63-32 Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsAcronym Register Description DDR VTP Register Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice