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manual Users Guide, TMS320DM643x DMP DDR2 Memory Controller
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TMS320DM643
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Specs
Functional Block Diagram
Clock Configuration
Connecting the DDR2 Memory Controller to DDR2 Memory
Reset Considerations
DDR2 SDRAM Commands
2.16.1 DDR2 Memory Controller Clock Stop Procedure
Signal Descriptions
Write recovery from autoprecharge. Value of
Power Management
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TMS320DM643x DMP
DDR2 Memory Controller
User's Guide
Literature Number: SPRU986B
November 2007
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Contents
TMS320DM643x DMP DDR2 Memory Controller
Users Guide
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SPRU986B-November
Contents
List of Figures
List of Figures
List of Tables
Preface
Read This First
About This Manual
Notational Conventions
Users Guide
DDR2 Memory Controller
1.2 Features
1 Introduction
1.4 Supported Use Case Statement
1.3 Functional Block Diagram
1.5 Industry Standards Compliance Statement
Figure 1. Data Paths to DDR2 Memory Controller
2 Peripheral Architecture
Figure 2. DDR2 Memory Controller Clock Block Diagram
2.1 Clock Control
2.1.1 Clock Source
Table 1. PLLC2 Configuration
2.1.2 Clock Configuration
2.2 Memory Map
2.1.3 DDR2 Memory Controller Internal Clock Domains
Figure 3. DDR2 Memory Controller Signals
2.3 Signal Descriptions
Table 2. DDR2 Memory Controller Signal Descriptions
Peripheral Architecture
Table 4. Truth Table for DDR2 SDRAM Commands
Table 3. DDR2 SDRAM Commands
2.4 Protocol Descriptions
Peripheral Architecture
Figure 4. Refresh Command
2.4.1 Refresh Mode
DDRCLK DDRCLK
DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30
2.4.2 Deactivation DCAB and DEAC
Figure 5. DCAB Command
DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10
DDRBA20 DDRDQM30
Peripheral Architecture
Figure 6. DEAC Command
DDR2 Memory Controller
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2.4.3 Activation ACTV
Figure 7. ACTV Command
DDRA120
Figure 8. DDR2 READ Command
2.4.4 READ Command
DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL
DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency
Figure 9. DDR2 WRT Command
2.4.5 Write WRT Command
Figure 10. DDR2 MRS and EMRS Command
2.4.6 Mode Register Set MRS and EMRS
Table 5. Addressable Memory Ranges
2.5 Memory Width and Byte Alignment
Figure 11. Byte Alignment
Table 6. 16-Bit External Memory
2.6 Endianness Considerations
Table 7. 32-Bit External Memory
2.7 Address Mapping
Table 8. Bank Configuration Register Fields for Address Mapping
Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM
Peripheral Architecture
DDR2 Memory Controller
Peripheral Architecture
Figure 12. Logical Address-to-DDR2 SDRAM Address Map
Peripheral Architecture
Figure 13. DDR2 SDRAM Column, Row, and Bank Access
DDR2 Memory Controller
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2.8 DDR2 Memory Controller Interface
Figure 14. DDR2 Memory Controller FIFO Block Diagram
Table 11. DDR2 Memory Controller FIFO Description
2.8.1 Command Ordering and Scheduling, Advanced Concept
2.8.3 Possible Race Condition
2.8.2 Command Starvation
2.9 Refresh Scheduling
2.10 Self-Refresh Mode
Table 12. Refresh Urgency Levels
Table 13. Reset Sources
2.11 Reset Considerations
Figure 15. DDR2 Memory Controller Reset Block Diagram
2.13 Auto-Initialization Sequence
2.12 VTP IO Buffer Calibration
Table 15. DDR2 SDRAM Configuration by EMRS1 Command
Table 14. DDR2 SDRAM Configuration by MRS Command
2.13.1 Initializing Configuration Registers
Write recovery from autoprecharge. Value of
2.13.2 Initializing Following Device Power Up and Device RESET
Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram
2.16 Power Management
2.14 Interrupt Support
2.15 DMA Event Support
2.17 Emulation Considerations
2.16.1 DDR2 Memory Controller Clock Stop Procedure
3 Supported Use Cases
3.1 Connecting the DDR2 Memory Controller to DDR2 Memory
Figure 18. Connecting DDR2 Memory Controller for 16-Bit Connection
Figure 17. Connecting DDR2 Memory Controller for 32-Bit Connection
Supported Use Cases
200 Ω 200 Ω
Table 16. SDRAM Bank Configuration Register SDBCR Configuration
3.2.1 Configuring SDRAM Bank Configuration Register SDBCR
3.2.2 Configuring SDRAM Refresh Control Register SDRCR
Table 17. DDR2 Memory Refresh Specification
Table 19. SDRAM Timing Register SDTIMR Configuration
3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2
Table 20. SDRAM Timing Register 2 SDTIMR2 Configuration
Table 21. DDR PHY Control Register DDRPHYCR Configuration
3.2.4 Configuring DDR PHY Control Register DDRPHYCR
4 DDR2 Memory Controller Registers
Figure 19. SDRAM Status Register SDRSTAT
4.1 SDRAM Status Register SDRSTAT
Table 25. SDRAM Status Register SDRSTAT Field Descriptions
Figure 20. SDRAM Bank Configuration Register SDBCR
4.2 SDRAM Bank Configuration Register SDBCR
Table 26. SDRAM Bank Configuration Register SDBCR Field Descriptions
DDR2 Memory Controller Registers
DDR2 Memory Controller
DDR2 Memory Controller Registers
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Figure 21. SDRAM Refresh Control Register SDRCR
4.3 SDRAM Refresh Control Register SDRCR
Table 27. SDRAM Refresh Control Register SDRCR Field Descriptions
DDR2 Memory Controller Registers
Figure 22. SDRAM Timing Register SDTIMR
4.4 SDRAM Timing Register SDTIMR
Table 28. SDRAM Timing Register SDTIMR Field Descriptions
DDR2 Memory Controller Registers
Figure 23. SDRAM Timing Register 2 SDTIMR2
4.5 SDRAM Timing Register 2 SDTIMR2
Table 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions
DDR2 Memory Controller Registers
Figure 24. Peripheral Bus Burst Priority Register PBBPR
4.6 Peripheral Bus Burst Priority Register PBBPR
Figure 25. Interrupt Raw Register IRR
4.7 Interrupt Raw Register IRR
Table 31. Interrupt Raw Register IRR Field Descriptions
DDR2 Memory Controller Registers
Figure 26. Interrupt Masked Register IMR
4.8 Interrupt Masked Register IMR
Table 32. Interrupt Masked Register IMR Field Descriptions
Figure 27. Interrupt Mask Set Register IMSR
4.9 Interrupt Mask Set Register IMSR
Table 33. Interrupt Mask Set Register IMSR Field Descriptions
DDR2 Memory Controller Registers
Figure 28. Interrupt Mask Clear Register IMCR
4.10 Interrupt Mask Clear Register IMCR
Table 34. Interrupt Mask Clear Register IMCR Field Descriptions
DDR2 Memory Controller Registers
Figure 29. DDR PHY Control Register DDRPHYCR
4.11 DDR PHY Control Register DDRPHYCR
Table 35. DDR PHY Control Register DDRPHYCR Field Descriptions
DDR2 Memory Controller Registers
Figure 30. VTP IO Control Register VTPIOCR
4.12 VTP IO Control Register VTPIOCR
Table 36. VTP IO Control Register VTPIOCR Field Descriptions
DDR2 Memory Controller Registers
Figure 32. DDR VTP Enable Register DDRVTPER
4.14 DDR VTP Enable Register DDRVTPER
Table 38. DDR VTP Enable Register DDRVTPER Field Descriptions
4.13 DDR VTP Register DDRVTPR
Table A-1. Document Revision History
Appendix A Revision History
Appendix A
Section
IMPORTANT NOTICE
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