Endianness Considerations | Texas Instruments TMS320DM643 instruction

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Peripheral Architecture

2.6Endianness Considerations

The DDR2 memory controller supports little-endian operating mode. This determines the order in which data on the internal data bus is written to or read from devices that are not as wide as the internal data bus. However, the DDR2 memory controller maintains the natural order of endian operations. That is, a stream of data starting at any address N will always be accessed in the correct or incrementing data order. The DDR2 memory controller will always access address N prior to N + 1 in any data width. Table 6 and Table 7 show operation of the DDR2 memory controller for both 16-bit and 32-bit external memory. See the device-specific data manual for the memory widths that are supported.

Table 6. 16-Bit External Memory

Internal Data (64-Bit	DDR_A[2:1]	DDR_D[15:0]
0123 4567 89AB CDEFh	00	CDEFh
0123 4567 89AB CDEFh	01	89ABh
0123 4567 89AB CDEFh	10	4567h
0123 4567 89AB CDEFh	11	0123h

Table 7. 32-Bit External Memory

Internal Data (64-Bit)	DDR_A[2]	DDR_D[31:0]
0123 4567 89AB CDEFh	0	89AB CDEFh
0123 4567 89AB CDEFh	1	0123 4567h

SPRU986B–November 2007	DDR2 Memory Controller	21
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Texas Instruments TMS320DM643 manual Endianness Considerations, Bit External Memory, Internal Data 64-Bit DDRA21 DDRD150

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral Features Functional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock Control PLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains DDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type Description Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Command Refresh Mode Deactivation Dcab and Deac Dcab Command Deac Command Activation Actv Actv Command DDR2 Read Command Read Command DDR2 WRT Command Write WRT Command DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Addressable Memory Ranges Memory Width and Byte Alignment Bit External Memory Endianness ConsiderationsInternal Data 64-Bit DDRA21 DDRD150 Internal Data 64-Bit DDRA2 DDRD310 Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept Possible Race Condition Command Starvation Refresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level Description Reset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer Calibration DDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 Memory Connecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Sdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula DDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D63-32 Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatAcronym Register Description DDR VTP Register Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register Sdrcr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2 Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRR Interrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMR Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register Imcr DDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register Ddrphycr VTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register Vtpiocr DDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Additions/Modifications/Deletions Table A-1. Document Revision History Important Notice