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Peripheral Architecture
2.13.2Initializing Following Device Power Up and Device RESET
CAUTION
The following
Following device power up, the DDR2 memory controller is held in reset with the internal clocks to the module gated off. Before releasing the DDR2 memory controller from reset, the clocks to the module must be turned on. Perform the following steps when turning the clocks on and initializing the module:
1.Program PLLC2 registers to provide a stable clock on PLL2_SYSCLK1 at the desired frequency.
2.Program the DDR2 memory controller Power and Sleep Controller (PSC) to enable VCLK.
3.Follow the register initialization procedure described in Section 2.13.1 to complete the DDR2 memory controller configuration.
4.Perform a dummy read of DDR2 memory to verify initialization sequence has completed.
5.Perform a soft reset of the DDR2 memory controller via the PSC using the following procedure. See the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978) for details on how to program the PSC.
a.To put the DDR2 memory controller into soft reset, program the PSC to place the DDR2 memory controller into the SyncReset state.
b.To take the DDR2 memory controller out of soft reset, program the PSC to place the DDR2 memory controller into the Enable state.
6.Enable VTP manual calibration by writing to the VTP IO control register (VTPIOCR). See Section 4.12 for details on VTPIOCR.
a.With a single write, set the EN bit field (bit 13) to 1 and the RECAL bit field (bit 15) to 0 by writing a value of 0000 201Fh.
b.Set the RECAL bit field (bit 15) to 1, making sure the value written to the EN field is still 1 by writing a value of 0000 A01Fh. This begins the calibration sequence.
7.Wait for a minimum of 33 VTP clk cycles for calibration to complete. The VTP clock operates at 13.5 MHZ.
8.Enable access to the DDR VTP register by writing a 1 to the DDR VTP enable register.
9.Read the DDR VTP register to get the P/N channel VTP value. See Section 4.13 for details on the DDR VTP register.
10.Write the VTP information to the PCH and NCH fields in the VTPIOCR. Make sure the RECAL and EN bits remain set to 1.
11.Write 0 to EN bit field in the VTP control register to disable VTP calibration.
12.Disable access to the DDR VTP register by writing a 0 to the DDR VTP enable register.
13.Disable VTP input clock by disabling the bypass clock of PLL2.
Note: If the DDR2 memory controller is reset via the Power and Sleep Controller (PSC) and the VTP input clock is disabled, accesses to the DDR2 memory controller will not complete. To
DDR2 Memory Controller | 33 |
