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Texas Instruments TMS320DM643 manual Interrupt Masked Register IMR

Models: TMS320DM643

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4.8Interrupt Masked Register (IMR)

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DDR2 Memory Controller Registers

4.8Interrupt Masked Register (IMR)

The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in Figure 26 and described in Table 32.

Figure 26. Interrupt Masked Register (IMR)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		LTM	Reserved
R-0		R/W1C-0		R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

			Table 32. Interrupt Masked Register (IMR) Field Descriptions
Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2	LTM		Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
			has no effect.
		0	A line trap condition has not occurred.
		1	Illegal memory access type (only set if the LTMSET bit in IMSR is set). See Section 2.14 for more
			details.
1-0	Reserved	0	Reserved

SPRU986B–November 2007	DDR2 Memory Controller	49
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Texas Instruments TMS320DM643 manual Interrupt Masked Register IMR Field Descriptions

Contents

TMS320DM643x DMP DDR2 Memory Controller Users GuideSubmit Documentation Feedback SPRU986B-NovemberContents List of Figures List of FiguresList of Tables Preface Read This FirstAbout This Manual Notational ConventionsUsers Guide DDR2 Memory Controller1.2 Features 1 Introduction1.4 Supported Use Case Statement 1.3 Functional Block Diagram1.5 Industry Standards Compliance Statement Figure 1. Data Paths to DDR2 Memory Controller2 Peripheral Architecture Figure 2. DDR2 Memory Controller Clock Block Diagram2.1 Clock Control 2.1.1 Clock SourceTable 1. PLLC2 Configuration 2.1.2 Clock Configuration2.2 Memory Map 2.1.3 DDR2 Memory Controller Internal Clock DomainsFigure 3. DDR2 Memory Controller Signals 2.3 Signal DescriptionsTable 2. DDR2 Memory Controller Signal Descriptions Peripheral ArchitectureTable 4. Truth Table for DDR2 SDRAM Commands Table 3. DDR2 SDRAM Commands2.4 Protocol Descriptions Peripheral ArchitectureFigure 4. Refresh Command 2.4.1 Refresh ModeDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM302.4.2 Deactivation DCAB and DEAC Figure 5. DCAB CommandDCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10 DDRBA20 DDRDQM30Peripheral Architecture Figure 6. DEAC CommandDDR2 Memory Controller Submit Documentation Feedback2.4.3 Activation ACTV Figure 7. ACTV CommandDDRA120 Figure 8. DDR2 READ Command 2.4.4 READ CommandDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL DDRBA20 BANK DDRA10 DDRDQM30 CAS LatencyFigure 9. DDR2 WRT Command 2.4.5 Write WRT CommandFigure 10. DDR2 MRS and EMRS Command 2.4.6 Mode Register Set MRS and EMRSTable 5. Addressable Memory Ranges 2.5 Memory Width and Byte AlignmentFigure 11. Byte Alignment Table 6. 16-Bit External Memory 2.6 Endianness ConsiderationsTable 7. 32-Bit External Memory 2.7 Address Mapping Table 8. Bank Configuration Register Fields for Address MappingTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMPeripheral Architecture DDR2 Memory ControllerPeripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address MapPeripheral Architecture Figure 13. DDR2 SDRAM Column, Row, and Bank AccessDDR2 Memory Controller Submit Documentation Feedback2.8 DDR2 Memory Controller Interface Figure 14. DDR2 Memory Controller FIFO Block DiagramTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.3 Possible Race Condition 2.8.2 Command Starvation2.9 Refresh Scheduling 2.10 Self-Refresh ModeTable 12. Refresh Urgency Levels Table 13. Reset Sources 2.11 Reset ConsiderationsFigure 15. DDR2 Memory Controller Reset Block Diagram 2.13 Auto-Initialization Sequence 2.12 VTP IO Buffer CalibrationTable 15. DDR2 SDRAM Configuration by EMRS1 Command Table 14. DDR2 SDRAM Configuration by MRS Command2.13.1 Initializing Configuration Registers Write recovery from autoprecharge. Value of2.13.2 Initializing Following Device Power Up and Device RESET Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.16 Power Management2.14 Interrupt Support 2.15 DMA Event Support2.17 Emulation Considerations 2.16.1 DDR2 Memory Controller Clock Stop Procedure3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 MemoryFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionSupported Use Cases 200 Ω 200 ΩTable 16. SDRAM Bank Configuration Register SDBCR Configuration 3.2.1 Configuring SDRAM Bank Configuration Register SDBCR3.2.2 Configuring SDRAM Refresh Control Register SDRCR Table 17. DDR2 Memory Refresh SpecificationTable 19. SDRAM Timing Register SDTIMR Configuration 3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2Table 20. SDRAM Timing Register 2 SDTIMR2 Configuration Table 21. DDR PHY Control Register DDRPHYCR Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCR4 DDR2 Memory Controller Registers Figure 19. SDRAM Status Register SDRSTAT 4.1 SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions Figure 20. SDRAM Bank Configuration Register SDBCR 4.2 SDRAM Bank Configuration Register SDBCRTable 26. SDRAM Bank Configuration Register SDBCR Field Descriptions DDR2 Memory Controller RegistersDDR2 Memory Controller DDR2 Memory Controller RegistersSubmit Documentation Feedback Figure 21. SDRAM Refresh Control Register SDRCR 4.3 SDRAM Refresh Control Register SDRCRTable 27. SDRAM Refresh Control Register SDRCR Field Descriptions DDR2 Memory Controller RegistersFigure 22. SDRAM Timing Register SDTIMR 4.4 SDRAM Timing Register SDTIMRTable 28. SDRAM Timing Register SDTIMR Field Descriptions DDR2 Memory Controller RegistersFigure 23. SDRAM Timing Register 2 SDTIMR2 4.5 SDRAM Timing Register 2 SDTIMR2Table 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions DDR2 Memory Controller RegistersFigure 24. Peripheral Bus Burst Priority Register PBBPR 4.6 Peripheral Bus Burst Priority Register PBBPRFigure 25. Interrupt Raw Register IRR 4.7 Interrupt Raw Register IRRTable 31. Interrupt Raw Register IRR Field Descriptions DDR2 Memory Controller RegistersFigure 26. Interrupt Masked Register IMR 4.8 Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions Figure 27. Interrupt Mask Set Register IMSR 4.9 Interrupt Mask Set Register IMSRTable 33. Interrupt Mask Set Register IMSR Field Descriptions DDR2 Memory Controller RegistersFigure 28. Interrupt Mask Clear Register IMCR 4.10 Interrupt Mask Clear Register IMCRTable 34. Interrupt Mask Clear Register IMCR Field Descriptions DDR2 Memory Controller RegistersFigure 29. DDR PHY Control Register DDRPHYCR 4.11 DDR PHY Control Register DDRPHYCRTable 35. DDR PHY Control Register DDRPHYCR Field Descriptions DDR2 Memory Controller RegistersFigure 30. VTP IO Control Register VTPIOCR 4.12 VTP IO Control Register VTPIOCRTable 36. VTP IO Control Register VTPIOCR Field Descriptions DDR2 Memory Controller RegistersFigure 32. DDR VTP Enable Register DDRVTPER 4.14 DDR VTP Enable Register DDRVTPERTable 38. DDR VTP Enable Register DDRVTPER Field Descriptions 4.13 DDR VTP Register DDRVTPRTable A-1. Document Revision History Appendix A Revision HistoryAppendix A SectionIMPORTANT NOTICE power.ti.comProducts Applications