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Texas Instruments TMS320DM643 manual Interrupt Mask Clear Register IMCR, DDR2 Memory Controller

Models: TMS320DM643

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4.10 Interrupt Mask Clear Register (IMCR)

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DDR2 Memory Controller Registers

4.10 Interrupt Mask Clear Register (IMCR)

The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 28 and described in Table 34.

Note: If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set register (IMSR), the interrupt is not enabled and neither bit is set to 1.

Figure 28. Interrupt Mask Clear Register (IMCR)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		LTMCLR	Reserved
R-0		R/W1C-0		R-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

Table 34. Interrupt Mask Clear Register (IMCR) Field Descriptions

Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2	LTMCLR		Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
			register (IMSR); a write of 0 has no effect.
		0	Line trap interrupt is not enabled.
		1	Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
1-0	Reserved	0	Reserved

SPRU986B–November 2007	DDR2 Memory Controller	51
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Texas Instruments TMS320DM643 Interrupt Mask Clear Register IMCR Field Descriptions, DDR2 Memory Controller Registers

Contents

TMS320DM643x DMP DDR2 Memory Controller Users GuideSubmit Documentation Feedback SPRU986B-NovemberContents List of Figures List of FiguresList of Tables Notational Conventions Read This FirstPreface About This Manual1 Introduction DDR2 Memory ControllerUsers Guide 1.2 FeaturesFigure 1. Data Paths to DDR2 Memory Controller 1.3 Functional Block Diagram1.4 Supported Use Case Statement 1.5 Industry Standards Compliance Statement2.1.1 Clock Source Figure 2. DDR2 Memory Controller Clock Block Diagram2 Peripheral Architecture 2.1 Clock Control2.1.3 DDR2 Memory Controller Internal Clock Domains 2.1.2 Clock ConfigurationTable 1. PLLC2 Configuration 2.2 Memory MapPeripheral Architecture 2.3 Signal DescriptionsFigure 3. DDR2 Memory Controller Signals Table 2. DDR2 Memory Controller Signal DescriptionsPeripheral Architecture Table 3. DDR2 SDRAM CommandsTable 4. Truth Table for DDR2 SDRAM Commands 2.4 Protocol DescriptionsDDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30 2.4.1 Refresh ModeFigure 4. Refresh Command DDRCLK DDRCLKDDRBA20 DDRDQM30 Figure 5. DCAB Command2.4.2 Deactivation DCAB and DEAC DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10Submit Documentation Feedback Figure 6. DEAC CommandPeripheral Architecture DDR2 Memory ControllerFigure 7. ACTV Command 2.4.3 Activation ACTVDDRA120 DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency 2.4.4 READ CommandFigure 8. DDR2 READ Command DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COLFigure 9. DDR2 WRT Command 2.4.5 Write WRT CommandFigure 10. DDR2 MRS and EMRS Command 2.4.6 Mode Register Set MRS and EMRS2.5 Memory Width and Byte Alignment Table 5. Addressable Memory RangesFigure 11. Byte Alignment 2.6 Endianness Considerations Table 6. 16-Bit External MemoryTable 7. 32-Bit External Memory 2.7 Address Mapping Table 8. Bank Configuration Register Fields for Address MappingDDR2 Memory Controller Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM Peripheral ArchitecturePeripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address MapSubmit Documentation Feedback Figure 13. DDR2 SDRAM Column, Row, and Bank AccessPeripheral Architecture DDR2 Memory ControllerFigure 14. DDR2 Memory Controller FIFO Block Diagram 2.8 DDR2 Memory Controller InterfaceTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.3 Possible Race Condition 2.8.2 Command Starvation2.10 Self-Refresh Mode 2.9 Refresh SchedulingTable 12. Refresh Urgency Levels 2.11 Reset Considerations Table 13. Reset SourcesFigure 15. DDR2 Memory Controller Reset Block Diagram 2.13 Auto-Initialization Sequence 2.12 VTP IO Buffer CalibrationWrite recovery from autoprecharge. Value of Table 14. DDR2 SDRAM Configuration by MRS CommandTable 15. DDR2 SDRAM Configuration by EMRS1 Command 2.13.1 Initializing Configuration Registers2.13.2 Initializing Following Device Power Up and Device RESET 2.15 DMA Event Support 2.16 Power ManagementFigure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.14 Interrupt Support2.17 Emulation Considerations 2.16.1 DDR2 Memory Controller Clock Stop Procedure3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory200 Ω 200 Ω Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection Supported Use CasesTable 17. DDR2 Memory Refresh Specification 3.2.1 Configuring SDRAM Bank Configuration Register SDBCRTable 16. SDRAM Bank Configuration Register SDBCR Configuration 3.2.2 Configuring SDRAM Refresh Control Register SDRCR3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2 Table 19. SDRAM Timing Register SDTIMR ConfigurationTable 20. SDRAM Timing Register 2 SDTIMR2 Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCR Table 21. DDR PHY Control Register DDRPHYCR Configuration4 DDR2 Memory Controller Registers 4.1 SDRAM Status Register SDRSTAT Figure 19. SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions DDR2 Memory Controller Registers 4.2 SDRAM Bank Configuration Register SDBCRFigure 20. SDRAM Bank Configuration Register SDBCR Table 26. SDRAM Bank Configuration Register SDBCR Field DescriptionsDDR2 Memory Controller Registers DDR2 Memory ControllerSubmit Documentation Feedback DDR2 Memory Controller Registers 4.3 SDRAM Refresh Control Register SDRCRFigure 21. SDRAM Refresh Control Register SDRCR Table 27. SDRAM Refresh Control Register SDRCR Field DescriptionsDDR2 Memory Controller Registers 4.4 SDRAM Timing Register SDTIMRFigure 22. SDRAM Timing Register SDTIMR Table 28. SDRAM Timing Register SDTIMR Field DescriptionsDDR2 Memory Controller Registers 4.5 SDRAM Timing Register 2 SDTIMR2Figure 23. SDRAM Timing Register 2 SDTIMR2 Table 29. SDRAM Timing Register 2 SDTIMR2 Field DescriptionsFigure 24. Peripheral Bus Burst Priority Register PBBPR 4.6 Peripheral Bus Burst Priority Register PBBPRDDR2 Memory Controller Registers 4.7 Interrupt Raw Register IRRFigure 25. Interrupt Raw Register IRR Table 31. Interrupt Raw Register IRR Field Descriptions4.8 Interrupt Masked Register IMR Figure 26. Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions DDR2 Memory Controller Registers 4.9 Interrupt Mask Set Register IMSRFigure 27. Interrupt Mask Set Register IMSR Table 33. Interrupt Mask Set Register IMSR Field DescriptionsDDR2 Memory Controller Registers 4.10 Interrupt Mask Clear Register IMCRFigure 28. Interrupt Mask Clear Register IMCR Table 34. Interrupt Mask Clear Register IMCR Field DescriptionsDDR2 Memory Controller Registers 4.11 DDR PHY Control Register DDRPHYCRFigure 29. DDR PHY Control Register DDRPHYCR Table 35. DDR PHY Control Register DDRPHYCR Field DescriptionsDDR2 Memory Controller Registers 4.12 VTP IO Control Register VTPIOCRFigure 30. VTP IO Control Register VTPIOCR Table 36. VTP IO Control Register VTPIOCR Field Descriptions4.13 DDR VTP Register DDRVTPR 4.14 DDR VTP Enable Register DDRVTPERFigure 32. DDR VTP Enable Register DDRVTPER Table 38. DDR VTP Enable Register DDRVTPER Field DescriptionsSection Appendix A Revision HistoryTable A-1. Document Revision History Appendix AApplications power.ti.comIMPORTANT NOTICE Products