Clock Generation and Control | Texas Instruments TMS320DM643X DMP

Peripheral Architecture

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2 Peripheral Architecture

2.1Clock Generation and Control

The UART bit clock is sourced from the PLLC1 AUXCLK. It supports up to 128 kbps maximum data rate.

Figure 2 is a conceptual clock generation diagram for the UART. The processor clock generator receives a signal from an external clock source and produces a UART input clock with a programmed frequency. The UART contains a programmable baud generator that takes an input clock and divides it by a divisor in the range between 1 and (216 - 1) to produce a baud clock (BCLK). The frequency of BCLK is sixteen times (16 ×) the baud rate; each received or transmitted bit lasts 16 BCLK cycles. When the UART is receiving, the bit is sampled in the 8th BCLK cycle. The formula to calculate the divisor is:

UART input clock frequency
Divisor + Desired baud rate 16	(1)

Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about these register fields, see Section 3. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value.

Figure 3 summarizes the relationship between the transferred data bit, BCLK, and the UART input clock.

Example baud rates and divisor values relative to a 27-MHz UART input clock are shown in Table 2.

DSP input clock

Figure 2. UART Clock Generation Diagram

Processor
		UART
			Receiver
		DLH:DLL	timing and
			control
Clock	UART input clock	Baud	BCLK
generator		generator
			Transmitter
			timing and
		Other logic	control
		Other logic

10	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Texas Instruments TMS320DM643X DMP manual Clock Generation and Control, Uart, Dlhdll, Bclk

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Purpose of the Peripheral Feature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance Statement Uart Block Diagram Fifo Dlhdll Clock Generation and ControlUart Bclk Baud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Parity STOP1 Endianness ConsiderationsData Format Parity Operation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow Control Autoflow Functional Timing Waveforms for RTS Loopback Control Initialization Reset ConsiderationsInterrupt Support Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions Comment DMA Event Support Power ManagementEmulation Considerations Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart Registers Receiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit Field Transmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Interrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt Source DMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1 Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions Dlab ST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB Bit Loop Modem Control Register MCRModem Control Register MCR Field Descriptions AFE Line Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBR Divisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field Descriptions CLS Peripheral Identification Registers PID1 and PID2CLS REV TYP Free Power and Emulation Management Register PwremumgmtUtrst Urrst Utrst Document Revision History Reference Additions/Modifications/Deletions Important Notice