Start Parity STOP1 STOP2 | Texas Instruments TMS320DM643X DMP

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Peripheral Architecture

Figure 3. Relationships Between Data Bit, BCLK, and UART Input Clock

n UART input clock cycles, where n = divisor in DLH:DLL

UART input clock

BCLK

TX,

Each bit lasts 16 BCLK cycles.

When receiving, the UART samples the bit in the 8th cycle.

TX,	START	D0	D1	D2	D3	D4	D5	D6	D7	PARITY STOP1 STOP2
RX

Table 2. Baud Rate Examples for 27 MHz UART Input Clock

Baud Rate	Divisor Value	Actual Baud Rate	Error (%)
2400	703	2400.427	0.018
4800	352	4794.034	-0.124
9600	176	9588.068	-0.124
19200	88	19176.14	-0.124
38400	44	38352.27	-0.124
56000	30	56250	0.446
128000	13	129807.7	1.412

SPRU997C –December 2009	Universal Asynchronous Receiver/Transmitter (UART)	11
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Texas Instruments TMS320DM643X DMP manual Baud Rate Examples for 27 MHz Uart Input Clock, Start Parity STOP1 STOP2

Contents

Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature Support Fifo Uart Block Diagram Bclk Clock Generation and ControlUart Dlhdll Start Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Parity Endianness ConsiderationsData Format Parity STOP1 Operation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Autoflow Control Uart Interface Using Autoflow Diagram Loopback Control Autoflow Functional Timing Waveforms for RTS Interrupt Support Reset ConsiderationsInitialization Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt Source Emulation Considerations Power ManagementDMA Event Support Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not Programmed Bit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field Descriptions Bit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei Erbi Interrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR Bits DMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr Fifoen Dlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLS STB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity Option AFE Modem Control Register MCRModem Control Register MCR Field Descriptions Loop Line Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSR Set Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLH Divisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field Descriptions TYP Peripheral Identification Registers PID1 and PID2CLS REV CLS Utrst Power and Emulation Management Register PwremumgmtUtrst Urrst Free Reference Additions/Modifications/Deletions Document Revision History Important Notice

Figure 3. Relationships Between Data Bit, BCLK, and UART Input Clock

BCLK

START

PARITY STOP1 STOP2

Table 2. Baud Rate Examples for 27 MHz UART Input Clock

Baud Rate

Divisor Value

Actual Baud Rate

Error (%)

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