Texas Instruments TMS320DM643X DMP guide

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Figure 17. Divisor LSB Latch (DLL)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			DLL

	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

			Table 18. Divisor LSB Latch (DLL) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	DLL	0-Fh	The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
			generator. Maximum baud rate is 128 kbps.

Figure 18. Divisor MSB Latch (DLH)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			DLH

	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

			Table 19. Divisor MSB Latch (DLH) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	DLH	0-Fh	The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
			generator. Maximum baud rate is 128 kbps.

34	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Texas Instruments TMS320DM643X DMP Divisor LSB Latch DLL Field Descriptions, Divisor MSB Latch DLH Field Descriptions

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Purpose of the Peripheral Feature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance Statement Uart Block Diagram Fifo Dlhdll Clock Generation and ControlUart Bclk Baud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Parity STOP1 Endianness ConsiderationsData Format Parity Operation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow Control Autoflow Functional Timing Waveforms for RTS Loopback Control Initialization Reset ConsiderationsInterrupt Support Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions Comment DMA Event Support Power ManagementEmulation Considerations Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart Registers Receiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit Field Transmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Interrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt Source DMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1 Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions Dlab ST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB Bit Loop Modem Control Register MCRModem Control Register MCR Field Descriptions AFE Line Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBR Divisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field Descriptions CLS Peripheral Identification Registers PID1 and PID2CLS REV TYP Free Power and Emulation Management Register PwremumgmtUtrst Urrst Utrst Document Revision History Reference Additions/Modifications/Deletions Important Notice