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Texas Instruments TMS320DM643X DMP manual List of Figures

Models: TMS320DM643X DMP

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	List of Figures
1	UART Block Diagram	9
2	UART Clock Generation Diagram	10
3	Relationships Between Data Bit, BCLK, and UART Input Clock	11
4	UART Protocol Formats	13
5	UART Interface Using Autoflow Diagram	16
6	Autoflow Functional Timing Waveforms for RTS	17
7	Autoflow Functional Timing Waveforms for CTS	17
8	UART Interrupt Request Enable Paths	19
9	Receiver Buffer Register (RBR)	22
10	Transmitter Holding Register (THR)	23
11	Interrupt Enable Register (IER)	24
12	Interrupt Identification Register (IIR)	25
13	FIFO Control Register (FCR)	27
14	Line Control Register (LCR)	28
15	Modem Control Register (MCR)	30
16	Line Status Register (LSR)	31
17	Divisor LSB Latch (DLL)	34
18	Divisor MSB Latch (DLH)	34
19	Peripheral Identification Register 1 (PID1)	35
20	Peripheral Identification Register 2 (PID2)	35
21	Power and Emulation Management Register (PWREMU_MGMT)	36

4	List of Figures	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Texas Instruments TMS320DM643X DMP manual List of Figures

Contents

Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Endianness Considerations Data FormatParity STOP1 ParityOperation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlInitialization Reset ConsiderationsInterrupt Support Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentDMA Event Support Power ManagementEmulation Considerations Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice