Submit Documentation Feedback | Texas Instruments TMS320DM643X DMP

2	SPRU997C –December 2009
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Texas Instruments TMS320DM643X DMP manual Submit Documentation Feedback

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Purpose of the Peripheral Feature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance Statement Uart Block Diagram Fifo Dlhdll Clock Generation and ControlUart Bclk Start Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Parity STOP1 Endianness ConsiderationsData Format Parity Operation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Uart Interface Using Autoflow Diagram Autoflow Control Autoflow Functional Timing Waveforms for RTS Loopback Control Interrupt Support Reset ConsiderationsInitialization Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions Comment Emulation Considerations Power ManagementDMA Event Support Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart Registers Receiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit Field Bit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Interrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt Source DMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1 Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions Dlab ST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB Bit Loop Modem Control Register MCRModem Control Register MCR Field Descriptions AFE Line Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBR Divisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field Descriptions CLS Peripheral Identification Registers PID1 and PID2CLS REV TYP Free Power and Emulation Management Register PwremumgmtUtrst Urrst Utrst Document Revision History Reference Additions/Modifications/Deletions Important Notice