Users Guide | Texas Instruments TMS320DM643X DMP instruction

TMS320DM643x DMP

Universal Asynchronous Receiver/Transmitter (UART)

User's Guide

Literature Number: SPRU997C

December 2009

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Texas Instruments TMS320DM643X DMP manual Users Guide

Contents

Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Purpose of the Peripheral Features Uart Supported Features/Characteristics by Instance Functional Block DiagramFeature Support Industry Standards Compliance Statement Fifo Uart Block Diagram Uart Clock Generation and ControlDlhdll Bclk Baud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Data Format Endianness ConsiderationsParity STOP1 Parity Operation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow Diagram Loopback Control Autoflow Functional Timing Waveforms for RTS Initialization Reset ConsiderationsInterrupt Support Uart Interrupt Requests Descriptions Enable bitsUart Interrupt Request Interrupt Source Comment DMA Event Support Power ManagementEmulation Considerations Exception Processing Changing Operating Mode During Busy Serial CommunicationDivisor Latch Not Programmed Uart Registers Receiver Buffer Register RBR Access considerationsReceiver Buffer Register RBR Field Descriptions Bit Field Transmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IERElsi Etbei Erbi Elsi Interrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Interrupt Identification and Interrupt Clearing Information Fifo Control Register FCRIIR Bits Interrupt Type Interrupt Source Rxfiftl Fifo Control Register FCR Field DescriptionsDMAMODE11 Txclr Rxclr Fifoen DMAMODE1 Line Control Register LCR Field Descriptions Line Control Register LCRDlab EPS PEN STB WLS Dlab Number of Stop Bits Generated Relationship Between ST, EPS, and PEN Bits in LCRST Bit EPS Bit PEN Bit Parity Option STB Bit Modem Control Register MCR Field Descriptions Modem Control Register MCRLoop AFE Fifo mode Non-FIFO modeLine Status Register LSR Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLH Divisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field Descriptions CLS REV Peripheral Identification Registers PID1 and PID2CLS TYP Utrst Urrst Power and Emulation Management Register PwremumgmtFree Utrst Reference Additions/Modifications/Deletions Document Revision History Important Notice