Functional Block Diagram | Texas Instruments TMS320DM643X DMP

Introduction

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Table 1 summarizes the capabilities supported on the UART. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details.

Table 1. UART Supported Features/Characteristics by Instance

Feature	Support
5, 6, 7 or 8-bit characters	Supported
Even, odd, or no PARITY bit	Supported
1, 1.5, or 2 STOP bit generation	Supported
Line break generation and detection	Supported
Internal loop back	Supported
DMA sync events for both received and transmitted data	Supported
1, 4, 8, or 14 byte selectable receiver FIFO trigger level	Supported
Polling/Interrupt	Supported
Max speed 128 kbps	Supported
Modem control functions using CTS and RTS	Supported(1)
Autoflow control using CTS and RTS	Supported(1)
DTR and DSR	Not supported
Ring indication	Not supported
Carrier detection	Not supported
Single-character transfer mode (mode 0) in DMA mode	Not supported

(1)Not supported on all UARTs. See the device-specific data manual for supported features.

1.3Functional Block Diagram

A functional block diagram of the UART is shown in Figure 1.

1.4Industry Standard(s) Compliance Statement

The UART peripheral is based on the industry standard TL16C550 asynchronous communications element, which is a functional upgrade of the TL16C450. Any deviations in supported functions are indicated in Table 1.

The information in this document assumes the reader is familiar with these standards.

8	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Texas Instruments TMS320DM643X DMP Functional Block Diagram, Industry Standards Compliance Statement, Feature Support

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance Statement Uart Block Diagram Fifo Clock Generation and Control UartDlhdll Bclk Start Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Endianness Considerations Data FormatParity STOP1 Parity Operation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Uart Interface Using Autoflow Diagram Autoflow Control Autoflow Functional Timing Waveforms for RTS Loopback Control Interrupt Support Reset ConsiderationsInitialization Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source Comment Emulation Considerations Power ManagementDMA Event Support Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart Registers Access considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit Field Bit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi Elsi Interrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt Source Fifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1 Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS Dlab Relationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB Bit Modem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFE Non-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBR Divisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field Descriptions Peripheral Identification Registers PID1 and PID2 CLS REVCLS TYP Power and Emulation Management Register Pwremumgmt Utrst UrrstFree Utrst Document Revision History Reference Additions/Modifications/Deletions Important Notice