Utrst Urrst, Free | Texas Instruments TMS320DM643X DMP instruction

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3.11 Power and Emulation Management Register (PWREMU_MGMT)

The power and emulation management register (PWREMU_MGMT) is shown in Figure 21 and described in Table 22.

Figure 21. Power and Emulation Management Register (PWREMU_MGMT)

31					16
				Reserved

				R-0
15	14	13	12	1	0

Rsvd	UTRST	URRST		Reserved	FREE

R/W-0	R/W-0	R/W-0		R-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 22. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15	Reserved	0	Reserved. This bit must always be written with a 0.

14	UTRST		UART transmitter reset. Resets and enables the transmitter.
		0	Transmitter is disabled and in reset state.
		1	Transmitter is enabled.

13	URRST		UART receiver reset. Resets and enables the receiver.
		0	Receiver is disabled and in reset state.
		1	Receiver is enabled.

12-1	Reserved	1	Reserved

0	FREE		Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When
			halted, the UART can handle register read/write requests, but does not generate any
			transmission/reception, interrupts or events.
		0	If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the
			UART halts after completion of the one-word transmission.
		1	Free-running mode is enabled; UART continues to run normally.

36	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Texas Instruments TMS320DM643X DMP manual Power and Emulation Management Register Pwremumgmt, Utrst Urrst, Free

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance Statement Uart Block Diagram Fifo Clock Generation and Control UartDlhdll Bclk Baud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Endianness Considerations Data FormatParity STOP1 Parity Operation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow Control Autoflow Functional Timing Waveforms for RTS Loopback Control Reset Considerations InitializationInterrupt Support Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source Comment Power Management DMA Event SupportEmulation Considerations Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart Registers Access considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit Field Transmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi Elsi Access consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt Source Fifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1 Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS Dlab Relationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB Bit Modem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFE Non-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field Descriptions Set Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBR Divisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field Descriptions Peripheral Identification Registers PID1 and PID2 CLS REVCLS TYP Power and Emulation Management Register Pwremumgmt Utrst UrrstFree Utrst Document Revision History Reference Additions/Modifications/Deletions Important Notice