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Xilinx PCI v3.0 Family Specific Considerations, 1 Device and Interface Selection Table Continued

Models: PCI v3.0

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Chapter 3: Family Specific Considerations

Table 3-1:Device and Interface Selection Table (Continued)

	Supported	Bus	Wrapper File	Constraints File/
	Device	Type	Wrapper File	Guide File
	Device	Type		Guide File

	2VP20-FF1152-6C/I	66 MHz	pcim_lc_66_3_s	2vp20ff1152_64_66.ucf
		3.3V		2vp20ff1152_64_66.ncd
		64-bit

	2VP20-FF1152-5C/I	33 MHz	pcim_lc_33_3_s	2vp20ff1152_64_33.ucf
		3.3V		no guide file
		64-bit

	2VP30-FF1152-6C/I	66 MHz	pcim_lc_66_3_s	2vp30ff1152_64_66.ucf
		3.3V		2vp30ff1152_64_66.ncd
		64-bit

	2VP30-FF1152-5C/I	33 MHz	pcim_lc_33_3_s	2vp30ff1152_64_33.ucf
		3.3V		no guide file
		64-bit

	2VP40-FF1152-6C/I	66 MHz	pcim_lc_66_3_s	2vp40ff1152_64_66.ucf
		3.3V		2vp40ff1152_64_66.ncd
		64-bit

	2VP40-FF1152-5C/I	33 MHz	pcim_lc_33_3_s	2vp40ff1152_64_33.ucf
		3.3V		no guide file
		64-bit

	2VP50-FF1152-6C/I	66 MHz	pcim_lc_66_3_s	2vp50ff1152_64_66.ucf
		3.3V		2vp50ff1152_64_66.ncd
		64-bit

	2VP50-FF1152-5C/I	33 MHz	pcim_lc_33_3_s	2vp50ff1152_64_33.ucf
		3.3V		no guide file
		64-bit

	3S1000-FG456-4C/I	33 MHz	pcim_lc_33_3_s	3s1000fg456_64_33.ucf
		3.3V		no guide file
		64-bit

	3S1200E-FG400-4C/I	33 MHz	pcim_lc_33_3_s	3s1200efg400_64_33.ucf
		3.3V		no guide file
		64-bit

	4VLX25-FF668-10C/I	33 MHz	pcim_lc_33_3_g	4vlx25ff668_64_33g.ucf
	global clock	3.3V		no guide file
		64-bit

22	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005

Image 22

Xilinx PCI v3.0 Family Specific Considerations, 1 Device and Interface Selection Table Continued, Supported, Wrapper File

Contents

Getting Started Guide UG157 August 31LogiCORE PCI v3.0.151Revision VersionPCI v3.0.151 Getting Started Guide UG157 August 31 Version Document → PDF SetupRevision PCI v3.0.151 Getting Started Guide UG157 August 31Preface About This Guide Table of ContentsChapter 2 Installing and Licensing the Core Chapter 1 Getting StartedChapter 7 Timing Simulation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design ISE FoundationAbout This Guide Guide ContentsPreface Typographical Additional ResourcesConventions Preface About This GuideItalic font Online DocumentConventions lowpwr =onoffPCI v3.0.151 Getting Started Guide Preface About This GuideUG157 August 31 About the Example Design Getting StartedChapter Additional DocumentationPCI Interface Core Technical SupportFeedback DocumentSystem Requirements Installing and Licensing the CoreInstalling the Core ChapterManual Installation CORE Generator IP Update CORE Generator IP Updates InstallerChapter 2 Installing and Licensing the Core Installing the Core Direct Download of Standalone CoreFull Licensing OptionsEvaluation Direct DownloadPCI v3.0.151 Getting Started Guide Installing Your License FileInstalling Your License File UG157 August 31PCI v3.0.151 Getting Started Guide Chapter 2 Installing and Licensing the CoreUG157 August 31 Table 3-1 Device and Interface Selection Table Family Specific ConsiderationsDesign Support SupportedSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileGuide Files Wrapper FilesConstraints Files Table 3-2 Guide File InformationDevice Initialization Table 3-2 Guide File Information Device InitializationBus Width Detection Figure 3-1 Sample SLOT64 GenerationInput Delay Buffers Datapath Output Clock EnableChapter 3 Family Specific Considerations Delay Setting Input Delay BuffersTable 3-3 Delay Buffer Settings ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsPackage Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces 64-bit InterfacesFF672 Bus Clock UsageFF668 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceSystem Supply Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION 3.3V PCI COMPLIANTGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation PCI v3.0.151 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG157 August 31 Cadence NC-Verilog Functional SimulationChapter Verilog Model Technology ModelSimChapter 4 Functional Simulation VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationFigure 5-5 Create a New Project Synthesizing a DesignSynplicity Synplify ChapterFigure 5-7 Select Files to Add Library Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowSynplicity Install Path/lib/xilinx Figure 5-8 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-9 Select Files to Add Dialog Box User Application Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source FilesSynplicity Synplify Figure 5-11 Options for Implementation Device16. Click OK to return to the main project window VHDL Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window Chapter 5 Synthesizing a DesignInstall Path/vhdl/src/xpci Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Xilinx XST Chapter 5 Synthesizing a DesignISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Chapter Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v Cadence NC-VerilogVerilog Chapter 7 Timing SimulationModel Technology ModelSim VHDLsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/pingtb.vhdPCI v3.0.151 Getting Started Guide Chapter 7 Timing SimulationUG157 August 31