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Xilinx Family Specific Considerations, PCI v3.0.151 Getting Started Guide, UG157 August 31

Models: PCI v3.0

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Chapter 3: Family Specific Considerations

This option is used to introduce additional delay on a global clock net. It is important to note that this additional delay is observable on the CLK output of the PCI interface, which is supplied to the user application. Timing constraints for the user application must be generated with this in mind.

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		UG157 August 31, 2005

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Xilinx manual Family Specific Considerations, PCI v3.0.151 Getting Started Guide, UG157 August 31

Contents

Getting Started Guide UG157 August 31LogiCORE PCI v3.0.151PCI v3.0.151 Getting Started Guide UG157 August 31 VersionRevision Revision Document → PDF SetupVersion PCI v3.0.151 Getting Started Guide UG157 August 31Preface About This Guide Table of ContentsChapter 2 Installing and Licensing the Core Chapter 1 Getting StartedChapter 7 Timing Simulation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design ISE FoundationPreface Guide ContentsAbout This Guide Typographical Additional ResourcesConventions Preface About This GuideItalic font Online DocumentConventions lowpwr =onoffUG157 August 31 Preface About This GuidePCI v3.0.151 Getting Started Guide About the Example Design Getting StartedChapter Additional DocumentationPCI Interface Core Technical SupportFeedback DocumentSystem Requirements Installing and Licensing the CoreInstalling the Core ChapterChapter 2 Installing and Licensing the Core CORE Generator IP Updates InstallerManual Installation CORE Generator IP Update Installing the Core Direct Download of Standalone CoreFull Licensing OptionsEvaluation Direct DownloadPCI v3.0.151 Getting Started Guide Installing Your License FileInstalling Your License File UG157 August 31UG157 August 31 Chapter 2 Installing and Licensing the CorePCI v3.0.151 Getting Started Guide Table 3-1 Device and Interface Selection Table Family Specific ConsiderationsDesign Support SupportedSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued Wrapper FileSupported Design SupportTable 3-1 Device and Interface Selection Table Continued Wrapper FileGuide Files Wrapper FilesConstraints Files Table 3-2 Guide File InformationDevice Initialization Table 3-2 Guide File Information Device InitializationBus Width Detection Figure 3-1 Sample SLOT64 GenerationChapter 3 Family Specific Considerations Datapath Output Clock EnableInput Delay Buffers Delay Setting Input Delay BuffersTable 3-3 Delay Buffer Settings ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsPackage Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces 64-bit InterfacesFF672 Bus Clock UsageFF668 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceSystem Supply Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION 3.3V PCI COMPLIANTFigure 3-4 Output Driver VCCO Generation Generating BitstreamsGenerating Bitstreams UG157 August 31 Chapter 3 Family Specific ConsiderationsPCI v3.0.151 Getting Started Guide Chapter Functional SimulationCadence NC-Verilog Chapter 4 Functional Simulation Model Technology ModelSimVerilog VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationFigure 5-5 Create a New Project Synthesizing a DesignSynplicity Synplify ChapterSynplicity Install Path/lib/xilinx Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowFigure 5-7 Select Files to Add Library Figure 5-9 Select Files to Add Dialog Box User Application Synplicity SynplifyFigure 5-8 Files to Add LogiCORE Files Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source Files16. Click OK to return to the main project window Figure 5-11 Options for Implementation DeviceSynplicity Synplify VHDL Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window Chapter 5 Synthesizing a DesignInstall Path/vhdl/src/xpci Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignFigure 5-17 Options for Implementation Exemplar LeonardoSpectrumExemplar LeonardoSpectrum Xilinx XST Chapter 5 Synthesizing a DesignChapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design Chapter Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v Cadence NC-VerilogVerilog Chapter 7 Timing SimulationModel Technology ModelSim VHDLsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/pingtb.vhdUG157 August 31 Chapter 7 Timing SimulationPCI v3.0.151 Getting Started Guide