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Xilinx PCI v3.0 manual Synplicity Synplify, 8 Files to Add LogiCORE Files

Models: PCI v3.0

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Synplicity Synplify

The next files are located in:

<Install Path>/verilog/src/xpci

6.Navigate to the xpci directory, select the simulation model and the wrapper files (pci_lc_i.v and pcim_lc.v), and click Add to move these files into the Files To Add list. (Ctrl-click to select multiple files.)

Figure 5-8:Files to Add (LogiCORE Files)

The final set of design files (the user application) is located in:

<Install Path>/verilog/example/source

7.Navigate to the source directory, select the cfg_ping.v, pcim_top.v, and ping.v files, and then click Add.

Figure 5-9:Select Files to Add Dialog Box (User Application)

PCI v3.0.151 Getting Started Guide

www.xilinx.com

UG157 August 31, 2005

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Xilinx PCI v3.0 Synplicity Synplify, 8 Files to Add LogiCORE Files, 9 Select Files to Add Dialog Box User Application

Contents

LogiCORE PCI UG157 August 31Getting Started Guide v3.0.151Version RevisionPCI v3.0.151 Getting Started Guide UG157 August 31 Document → PDF Setup VersionRevision UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 2 Installing and Licensing the Core Table of ContentsPreface About This Guide Chapter 1 Getting StartedChapter 6 Implementing a Design Chapter 5 Synthesizing a DesignChapter 7 Timing Simulation ISE FoundationGuide Contents About This GuidePreface Conventions Additional ResourcesTypographical Preface About This GuideConventions Online DocumentItalic font lowpwr =onoffPreface About This Guide PCI v3.0.151 Getting Started GuideUG157 August 31 Chapter Getting StartedAbout the Example Design Additional DocumentationFeedback Technical SupportPCI Interface Core DocumentInstalling the Core Installing and Licensing the CoreSystem Requirements ChapterCORE Generator IP Updates Installer Manual Installation CORE Generator IP UpdateChapter 2 Installing and Licensing the Core Direct Download of Standalone Core Installing the CoreEvaluation Licensing OptionsFull Direct DownloadInstalling Your License File Installing Your License FilePCI v3.0.151 Getting Started Guide UG157 August 31Chapter 2 Installing and Licensing the Core PCI v3.0.151 Getting Started GuideUG157 August 31 Design Support Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table SupportedTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileConstraints Files Wrapper FilesGuide Files Table 3-2 Guide File InformationBus Width Detection Device InitializationDevice Initialization Table 3-2 Guide File Information Figure 3-1 Sample SLOT64 GenerationDatapath Output Clock Enable Input Delay BuffersChapter 3 Family Specific Considerations Table 3-3 Delay Buffer Settings Input Delay BuffersDelay Setting ImplementationChapter 3 Family Specific Considerations Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces Regional Clock UsagePackage 64-bit InterfacesFF668 Bus Clock UsageFF672 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceREGION Figure 3-3 Relationship For 3.3V Input Buffer ComplianceSystem Supply 3.3V PCI COMPLIANTGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation Chapter 3 Family Specific Considerations PCI v3.0.151 Getting Started GuideUG157 August 31 Functional Simulation Cadence NC-VerilogChapter Model Technology ModelSim VerilogChapter 4 Functional Simulation Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimSynplicity Synplify Synthesizing a DesignFigure 5-5 Create a New Project ChapterChapter 5 Synthesizing a Design Figure 5-6 Main Project Window Figure 5-7 Select Files to Add LibrarySynplicity Install Path/lib/xilinx Synplicity Synplify Figure 5-8 Files to Add LogiCORE FilesFigure 5-9 Select Files to Add Dialog Box User Application Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a DesignFigure 5-11 Options for Implementation Device Synplicity Synplify16. Click OK to return to the main project window Figure 5-13 Main Project Window Figure 5-12 Create a New ProjectVHDL Chapter 5 Synthesizing a DesignFigure 5-15 Select Files to Add LogiCORE Files Figure 5-14 Select Files to Add LibraryInstall Path/vhdl/src/xpci Synplicity SynplifyChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Chapter 5 Synthesizing a Design Xilinx XSTImplementing a Design ISE FoundationChapter Chapter 6 Implementing a Design cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v Timing SimulationChapter Cadence NC-VerilogModel Technology ModelSim Chapter 7 Timing SimulationVerilog VHDLpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd Model Technology ModelSimsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd source/pingtb.vhdChapter 7 Timing Simulation PCI v3.0.151 Getting Started GuideUG157 August 31