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Xilinx PCI v3.0 manual Implementing a Design, ISE Foundation, Chapter

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Implementing a Design

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Chapter 6

Implementing a Design

This chapter describes how to implement the ping64 example design with global clocks using the supported FPGA implementation tools (included with the ISE Foundation v7.1 Development System). For the PCI 32 interface, substitute ping32 for ping64. If you are using a design with reference clocks, substitute pcim_top with pcim_top_r and ping_tb with ping_tb_r.

ISE Foundation

Before implementing a design, ensure that the Xilinx environment is properly configured and the design has been successfully synthesized.

1.Navigate to the implementation directory: cd <Install Path>/hdl/example/xilinx

This directory contains the run_xilinx script that calls the appropriate tools to place and route the example design. Scripts are provided for Unix and Microsoft Windows operating systems.

2.Review the appropriate run_xilinx script file, noting the following:

•Several required special environment variables are set at the beginning of the script; do not remove them.

•The ngdbuild command lists both ../../src/xpci search directories. The xpci directory contains a netlist the synthesis directory must contain the EDIF netlist synthesis.

and ../synthesis as of the PCI interface, and generated during design

The ngdbuild command also reads a user constraints file that corresponds to a desired target device and a particular version of the PCI interface.

•To target a different device or to use a different version of the PCI interface, the constraints file must be changed to match the device and interface selection. The available selections are defined in Chapter 3, “Family Specific Considerations.”

The user constraints files provided with the PCI interface include constraints that guarantee pinout and timing specifications. These constraints must always be used during processing.

Additional constraints that relate to the user application must be placed in this file. Before making additions to the user constraints file, back up the original so that it can be restored if necessary.

•The map command requires no special arguments, but uses an input/output register packing option.

PCI v3.0.151 Getting Started Guide

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UG157 August 31, 2005

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Xilinx PCI v3.0 manual Implementing a Design, ISE Foundation, Chapter

Contents

LogiCORE PCI UG157 August 31Getting Started Guide v3.0.151PCI v3.0.151 Getting Started Guide UG157 August 31 VersionRevision Revision Document → PDF SetupVersion UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 2 Installing and Licensing the Core Table of ContentsPreface About This Guide Chapter 1 Getting StartedChapter 6 Implementing a Design Chapter 5 Synthesizing a DesignChapter 7 Timing Simulation ISE FoundationPreface Guide ContentsAbout This Guide Conventions Additional ResourcesTypographical Preface About This GuideConventions Online DocumentItalic font lowpwr =onoffUG157 August 31 Preface About This GuidePCI v3.0.151 Getting Started Guide Chapter Getting StartedAbout the Example Design Additional DocumentationFeedback Technical SupportPCI Interface Core DocumentInstalling the Core Installing and Licensing the CoreSystem Requirements ChapterChapter 2 Installing and Licensing the Core CORE Generator IP Updates InstallerManual Installation CORE Generator IP Update Direct Download of Standalone Core Installing the CoreEvaluation Licensing OptionsFull Direct DownloadInstalling Your License File Installing Your License FilePCI v3.0.151 Getting Started Guide UG157 August 31UG157 August 31 Chapter 2 Installing and Licensing the CorePCI v3.0.151 Getting Started Guide Design Support Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table SupportedTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Chapter 3 Family Specific ConsiderationsSupported Wrapper FileTable 3-1 Device and Interface Selection Table Continued Design SupportSupported Wrapper FileConstraints Files Wrapper FilesGuide Files Table 3-2 Guide File InformationBus Width Detection Device InitializationDevice Initialization Table 3-2 Guide File Information Figure 3-1 Sample SLOT64 GenerationChapter 3 Family Specific Considerations Datapath Output Clock EnableInput Delay Buffers Table 3-3 Delay Buffer Settings Input Delay BuffersDelay Setting ImplementationChapter 3 Family Specific Considerations Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces Regional Clock UsagePackage 64-bit InterfacesFF668 Bus Clock UsageFF672 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceREGION Figure 3-3 Relationship For 3.3V Input Buffer ComplianceSystem Supply 3.3V PCI COMPLIANTFigure 3-4 Output Driver VCCO Generation Generating BitstreamsGenerating Bitstreams UG157 August 31 Chapter 3 Family Specific ConsiderationsPCI v3.0.151 Getting Started Guide Chapter Functional SimulationCadence NC-Verilog Chapter 4 Functional Simulation Model Technology ModelSimVerilog Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimSynplicity Synplify Synthesizing a DesignFigure 5-5 Create a New Project ChapterSynplicity Install Path/lib/xilinx Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowFigure 5-7 Select Files to Add Library Figure 5-9 Select Files to Add Dialog Box User Application Synplicity SynplifyFigure 5-8 Files to Add LogiCORE Files Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a Design16. Click OK to return to the main project window Figure 5-11 Options for Implementation DeviceSynplicity Synplify Figure 5-13 Main Project Window Figure 5-12 Create a New ProjectVHDL Chapter 5 Synthesizing a DesignFigure 5-15 Select Files to Add LogiCORE Files Figure 5-14 Select Files to Add LibraryInstall Path/vhdl/src/xpci Synplicity SynplifyChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesFigure 5-17 Options for Implementation Exemplar LeonardoSpectrumExemplar LeonardoSpectrum Chapter 5 Synthesizing a Design Xilinx XSTChapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v Timing SimulationChapter Cadence NC-VerilogModel Technology ModelSim Chapter 7 Timing SimulationVerilog VHDLpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd Model Technology ModelSimsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd source/pingtb.vhdUG157 August 31 Chapter 7 Timing SimulationPCI v3.0.151 Getting Started Guide