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Xilinx PCI v3.0 manual Xilinx XST, Synthesizing a Design

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Chapter 5: Synthesizing a Design

The end result of the synthesis step is an EDIF file that is fed into the Xilinx implementation tools during the implementation step.

In practice, the provided script file must be modified to accommodate other designs. To provide insight into the synthesis script, the major steps are presented below:

1.Various synthesis options are set through the use of environment variables. These must be present in the script, and should not be modified. The synthesis library is also loaded; this may be altered for different devices and speed grades.

2.The design is loaded by reading in the design files. At this point, the top-level module is declared as the present_design. The script adds nopad attributes (with a value of FALSE) to all PCI bus interface signals. The I/O structures for these ports are directly instantiated in the wrapper file.

3.The optimization step is done with the -hierarchy preserve and the -chipoptions. The -hierarchy preserve option prevents LeonardoSpectrum from dissolving the design hierarchy. The -chipoption indicates that automatic I/O buffer insertion should be performed.

4.After synthesis is complete, the synthesized netlist is written.

5.The tool may issue warnings about unused signals; these warnings are expected.

Xilinx XST

Before attempting to synthesize a design, ensure that the Xilinx XST environment is properly configured. Synthesis is supported only from the XST command line.

1.Navigate to the synthesis directory:

cd <Install Path>/hdl/example/synthesis

The synthesis directory contains a script for use with Xilinx XST; this script is called run_xst.bat for PC platforms and run_xst.csh for Unix platforms. Note that the run_xst.cmd and run_xst.prj files are common and used by both scripts.

2.If required, modify the files as required to suit your application. You may need to change the target architecture and select different wrapper and configuration files.

3.Synthesize the design by running the script.

The end result of the synthesis step is an NGC file that is fed into the Xilinx implementation tools during the implementation step. The tool may issue warnings about unused signals; these warnings are expected.

52	www.xilinx.com	PCI v3.0.151 Getting Started Guide
		UG157 August 31, 2005

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Xilinx PCI v3.0 manual Xilinx XST, Synthesizing a Design

Contents

UG157 August 31 LogiCORE PCIGetting Started Guide v3.0.151Revision VersionPCI v3.0.151 Getting Started Guide UG157 August 31 Version Document → PDF SetupRevision PCI v3.0.151 Getting Started Guide UG157 August 31Table of Contents Chapter 2 Installing and Licensing the CorePreface About This Guide Chapter 1 Getting StartedChapter 5 Synthesizing a Design Chapter 6 Implementing a DesignChapter 7 Timing Simulation ISE FoundationAbout This Guide Guide ContentsPreface Additional Resources ConventionsTypographical Preface About This GuideOnline Document ConventionsItalic font lowpwr =onoffPCI v3.0.151 Getting Started Guide Preface About This GuideUG157 August 31 Getting Started ChapterAbout the Example Design Additional DocumentationTechnical Support FeedbackPCI Interface Core DocumentInstalling and Licensing the Core Installing the CoreSystem Requirements ChapterManual Installation CORE Generator IP Update CORE Generator IP Updates InstallerChapter 2 Installing and Licensing the Core Installing the Core Direct Download of Standalone CoreLicensing Options EvaluationFull Direct DownloadInstalling Your License File Installing Your License FilePCI v3.0.151 Getting Started Guide UG157 August 31PCI v3.0.151 Getting Started Guide Chapter 2 Installing and Licensing the CoreUG157 August 31 Family Specific Considerations Design SupportTable 3-1 Device and Interface Selection Table SupportedChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileChapter 3 Family Specific Considerations Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileDesign Support Table 3-1 Device and Interface Selection Table ContinuedSupported Wrapper FileWrapper Files Constraints FilesGuide Files Table 3-2 Guide File InformationDevice Initialization Bus Width DetectionDevice Initialization Table 3-2 Guide File Information Figure 3-1 Sample SLOT64 GenerationInput Delay Buffers Datapath Output Clock EnableChapter 3 Family Specific Considerations Input Delay Buffers Table 3-3 Delay Buffer SettingsDelay Setting ImplementationRegional Clock Usage Chapter 3 Family Specific ConsiderationsRegional Clock Usage Table 3-4 Virtex-4 Device and Package 64-bit InterfacesPackage 64-bit InterfacesBus Clock Usage FF668FF672 Chapter 3 Family Specific ConsiderationsElectrical Compliance Electrical ComplianceFigure 3-3 Relationship For 3.3V Input Buffer Compliance REGIONSystem Supply 3.3V PCI COMPLIANTGenerating Bitstreams Generating BitstreamsFigure 3-4 Output Driver VCCO Generation PCI v3.0.151 Getting Started Guide Chapter 3 Family Specific ConsiderationsUG157 August 31 Cadence NC-Verilog Functional SimulationChapter Verilog Model Technology ModelSimChapter 4 Functional Simulation VHDL Model Technology ModelSimInstall Path/vhdl/example/funcsim Chapter 4 Functional SimulationSynthesizing a Design Synplicity SynplifyFigure 5-5 Create a New Project ChapterFigure 5-7 Select Files to Add Library Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowSynplicity Install Path/lib/xilinx Figure 5-8 Files to Add LogiCORE Files Synplicity SynplifyFigure 5-9 Select Files to Add Dialog Box User Application Chapter 5 Synthesizing a Design Figure 5-10 Main Project Window with Source FilesSynplicity Synplify Figure 5-11 Options for Implementation Device16. Click OK to return to the main project window Figure 5-12 Create a New Project Figure 5-13 Main Project WindowVHDL Chapter 5 Synthesizing a DesignFigure 5-14 Select Files to Add Library Figure 5-15 Select Files to Add LogiCORE FilesInstall Path/vhdl/src/xpci Synplicity SynplifyFigure 5-16 Project Window with Source Files Chapter 5 Synthesizing a DesignExemplar LeonardoSpectrum Exemplar LeonardoSpectrumFigure 5-17 Options for Implementation Xilinx XST Chapter 5 Synthesizing a DesignISE Foundation Implementing a DesignChapter Chapter 6 Implementing a Design Timing Simulation cd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.vChapter Cadence NC-VerilogChapter 7 Timing Simulation Model Technology ModelSimVerilog VHDLModel Technology ModelSim pcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhdsource/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhd source/pingtb.vhdPCI v3.0.151 Getting Started Guide Chapter 7 Timing SimulationUG157 August 31