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Xilinx PCI v3.0 manual 11 Options for Implementation Device, Synplicity Synplify

Models: PCI v3.0

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Figure 5-11:Options for Implementation: Device

Synplicity Synplify

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Figure 5-11:Options for Implementation: Device

13.On the Device tab, set the Technology, Part, Speed, and Package options to reflect the targeted device (a V300BG432-6 in this example). Be sure that Disable I/O Insertion is deselected.

14.On the Options/Constraints tab, deselect Symbolic FSM Compiler (but leave Resource Sharing selected) and set the Frequency to 66 MHz.

15.On the Implementation Results tab, deselect Write Vendor Constraint File.

16.Click OK to return to the main project window.

17.From the main project window, click Run.

Synplify synthesizes the design and writes out an optimized EDIF file. In the lower- right corner of the window, the various stages or synthesis, such as Compiling or Mapping, are displayed. When the process is complete, Done is displayed. Note that Synplify may issue a number of warnings (are expected) about instantiated I/O cells and attributes used for other synthesis tools.

PCI v3.0.151 Getting Started Guide

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UG157 August 31, 2005

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Xilinx PCI v3.0 11 Options for Implementation Device, Synplicity Synplify, Click OK to return to the main project window

Contents

v3.0.151 UG157 August 31LogiCORE PCI Getting Started GuidePCI v3.0.151 Getting Started Guide UG157 August 31 VersionRevision Revision Document → PDF SetupVersion UG157 August 31 PCI v3.0.151 Getting Started GuideChapter 1 Getting Started Table of ContentsChapter 2 Installing and Licensing the Core Preface About This GuideISE Foundation Chapter 5 Synthesizing a DesignChapter 6 Implementing a Design Chapter 7 Timing SimulationPreface Guide ContentsAbout This Guide Preface About This Guide Additional ResourcesConventions Typographicallowpwr =onoff Online DocumentConventions Italic fontUG157 August 31 Preface About This GuidePCI v3.0.151 Getting Started Guide Additional Documentation Getting StartedChapter About the Example DesignDocument Technical SupportFeedback PCI Interface CoreChapter Installing and Licensing the CoreInstalling the Core System RequirementsChapter 2 Installing and Licensing the Core CORE Generator IP Updates InstallerManual Installation CORE Generator IP Update Direct Download of Standalone Core Installing the CoreDirect Download Licensing OptionsEvaluation FullUG157 August 31 Installing Your License FileInstalling Your License File PCI v3.0.151 Getting Started GuideUG157 August 31 Chapter 2 Installing and Licensing the CorePCI v3.0.151 Getting Started Guide Supported Family Specific ConsiderationsDesign Support Table 3-1 Device and Interface Selection TableWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Chapter 3 Family Specific ConsiderationsTable 3-1 Device and Interface Selection Table Continued SupportedWrapper File Design SupportTable 3-1 Device and Interface Selection Table Continued SupportedTable 3-2 Guide File Information Wrapper FilesConstraints Files Guide FilesFigure 3-1 Sample SLOT64 Generation Device InitializationBus Width Detection Device Initialization Table 3-2 Guide File InformationChapter 3 Family Specific Considerations Datapath Output Clock EnableInput Delay Buffers Implementation Input Delay BuffersTable 3-3 Delay Buffer Settings Delay SettingChapter 3 Family Specific Considerations Regional Clock Usage64-bit Interfaces Regional Clock UsageTable 3-4 Virtex-4 Device and Package 64-bit Interfaces PackageChapter 3 Family Specific Considerations Bus Clock UsageFF668 FF672Electrical Compliance Electrical Compliance3.3V PCI COMPLIANT Figure 3-3 Relationship For 3.3V Input Buffer ComplianceREGION System SupplyFigure 3-4 Output Driver VCCO Generation Generating BitstreamsGenerating Bitstreams UG157 August 31 Chapter 3 Family Specific ConsiderationsPCI v3.0.151 Getting Started Guide Chapter Functional SimulationCadence NC-Verilog Chapter 4 Functional Simulation Model Technology ModelSimVerilog Model Technology ModelSim VHDLChapter 4 Functional Simulation Install Path/vhdl/example/funcsimChapter Synthesizing a DesignSynplicity Synplify Figure 5-5 Create a New ProjectSynplicity Install Path/lib/xilinx Chapter 5 Synthesizing a Design Figure 5-6 Main Project WindowFigure 5-7 Select Files to Add Library Figure 5-9 Select Files to Add Dialog Box User Application Synplicity SynplifyFigure 5-8 Files to Add LogiCORE Files Figure 5-10 Main Project Window with Source Files Chapter 5 Synthesizing a Design16. Click OK to return to the main project window Figure 5-11 Options for Implementation DeviceSynplicity Synplify Chapter 5 Synthesizing a Design Figure 5-12 Create a New ProjectFigure 5-13 Main Project Window VHDLSynplicity Synplify Figure 5-14 Select Files to Add LibraryFigure 5-15 Select Files to Add LogiCORE Files Install Path/vhdl/src/xpciChapter 5 Synthesizing a Design Figure 5-16 Project Window with Source FilesFigure 5-17 Options for Implementation Exemplar LeonardoSpectrumExemplar LeonardoSpectrum Chapter 5 Synthesizing a Design Xilinx XSTChapter Implementing a DesignISE Foundation Chapter 6 Implementing a Design Cadence NC-Verilog Timing Simulationcd Install Path/verilog/example/postsim cp ../xilinx/pcimtoprouted.v ChapterVHDL Chapter 7 Timing SimulationModel Technology ModelSim Verilogsource/pingtb.vhd Model Technology ModelSimpcimtoprouted.vhd source/busrecord.vhd source/dumbarbiter.vhd source/dumbtarg32.vhd source/dumbtarg64.vhd source/stimulus.vhdUG157 August 31 Chapter 7 Timing SimulationPCI v3.0.151 Getting Started Guide